Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.6. Setup Elements

This development board includes several different kinds of setup elements. This section describes the following setup elements:
  • JTAG Chain Device removal switch
  • Program Select pushbutton
  • MAX® V Reset pushbutton
  • CPU Reset pushbutton

JTAG Chain Device Removal Switch

The JTAG chain connects the Intel® Stratix® 10 GX FPGA, the MAX® V CPLD, FMC A and FMC B in a chain, with the option to selectively bypass each JTAG node by four dip switch setting.

Program Select Pushbutton

After a POWER-ON or RESET (reconfiguration) event, the MAX® V configures the Intel® Stratix® 10 GX FPGA in the AvST mode with either the FACTORY POF or a USER-DEFINED POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this pushbutton and observing the program LEDs (FACTORY or USER) dictates the program selection. Then, the PGM_CONFIG pushbutton must be pressed to load the program.

MAX® V Reset Pushbutton

This pushbutton is the development board's Master Reset. This pushbuttton is connected to the MAX® V CPLD (MAX_RESETn pin) that is used for AvST configuration. When this button is pressed, the MAX® V CPLD initiates a reloading of the stored image from flash memory using AvST configuration mode. The image that is reloaded depends on the PGMSEL setting.

CPU Reset Pushbutton

This pushbutton is the Nios® II CPU Reset. This button is connected to a Intel® Stratix® 10 GX FPGA global signal input pin and can be used by Nios® II implementations as a dedicated CPU Reset button. This button is also connected to the MAX® V CPLD so that the FPGA device can be reset right after its configuration with AvST mode.

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