7. Board Update Portal
The Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board. The design consists of a Nios® II embedded processor, an Ethernet MAC and an HTML web server.
When you power up the board with the SW6.1 FACTORY_LOAD to OFF(1) position, Intel® Stratix® 10 GX FPGA configures with the Board Update Portal design example. The design can obtain an IP address from any DHCP server and serve a webpage from the flash on your board to any host computer on the same network. The webpage allows you to upload a new FPGA design to the user portion of flash memory and provides links to useful information on the Intel® website, including kit-specific links and design resources.
After successfully updating the user flash memory, you can load the user design from flash memory into the FPGA by setting SW6.1 to ON(0) position and power cycle the board. The source code for the Board Update Portal resides in the <package dir>\examples\board_update_portal directory.
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