Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.11. Flash Memory

The development board has two 1-Gbit CFI compatible synchronous flash device for non-voltaile storage of the FPGA configuration data, board information, test application data and user code space.

Two flash devices are implemented to achieve a 32-bit wide data bus at 16 bits each per device. The target device is a Micron PC28F00AP30BF CFI Flash device. Both MAX® V CPLD and Intel® Stratix® 10 GX FPGA can access this Flash device.

MAX® V CPLD accesses are for AvST configuration of the FPGA at power-on and board reset events. It uses the PFL Megafunction. Intel® Stratix® 10 GX FPGA access to the flash memory's user space is done by Nios® II for the BUP application. The flash is wired for WORD mode operation to support AvSTx32 download directly.

The table below shows the memory map for the on-board flash. This memory provides non-volatile storage for two FPGA bit-streams as well as various settings for data used for the Board Update Portal (BUP) image and on-board devices such as PFL II configuration bits.

Table 22.  Flash Memory Map
Block Description Size Address
Board Test System 512 KB 0x09F4.0000 - 09FB.FFFF
User Software 14,336 KB 0x0914.0000 - 09F3.FFFF
Factory Software 8,192 KB 0x0894.0000 - 0913.FFFF
zipfs 8,192 KB 0x0814.0000 -0893.FFFF
User Hardware 2 44,032 KB 0x0564.0000 - 0813.FFFF
User Hardware 1 44,032 KB 0x02B4.0000 - 0563.FFFF
Factory Hardware 44,032 KB 0x0004.0000 - 02B3.FFFF
PFL Option Bits 64 KB 0x0003.0000 - 0003.FFFF
Board Information 64 KB 0x0002.0000 - 0002.FFFF
Ethernet Option Bits 64 KB 0x0001.0000 - 0001.FFFF
User Design Reset 64 KB 0x0000.0000 - 0000.FFFF

Each FPGA bit-stream can be a maximum of 254.25 Mbits (or less than 32 MB) for the Intel® Stratix® 10 GX FPGA device. The remaining area is designated as RESERVED flash area for storage of the BUP image and PFL configuration settings, software binaries and other data relevant to the FPGA design.

Table 23.  Flash Memory Pin Assignments Table
Flash Memory Device Pin Number (U33/U34) Schematic Signal Name Description Intel® Stratix® 10 Device Pin Number
A1 (U33/U34) FM_A1 Address Bus BB30
B1 (U33/U34) FM_A2 Address Bus BF31
C1 (U33/U34) FM_A3 Address Bus BG32
D1 (U33/U34) FM_A4 Address Bus BC35
D2 (U33/U34) FM_A5 Address Bus BG29
A2 (U33/U34) FM_A6 Address Bus BG30
C2 (U33/U34) FM_A7 Address Bus BH28
A3 (U33/U34) FM_A8 Address Bus BH31
B3 (U33/U34) FM_A9 Address Bus BF29
C3 (U33/U34) FM_A10 Address Bus BH32
D3 (U33/U34) FM_A11 Address Bus BD29
C4 (U33/U34) FM_A12 Address Bus BC36
A5 (U33/U34) FM_A13 Address Bus BA31
B5 (U33/U34) FM_A14 Address Bus BJ29
C5 (U33/U34) FM_A15 Address Bus BJ30
D7 (U33/U34) FM_A16 Address Bus BA32
D8 (U33/U34) FM_A17 Address Bus BE28
A7 (U33/U34) FM_A18 Address Bus AU30
B7 (U33/U34) FM_A19 Address Bus AT30
C7 (U33/U34) FM_A20 Address Bus BJ28
C8 (U33/U34) FM_A21 Address Bus BG28
A8 (U33/U34) FM_A22 Address Bus BE29
G1 (U33/U34) FM_A23 Address Bus BD36
H8 (U33/U34) FM_A24 Address Bus BH30
B6 (U33/U34) FM_A25 Address Bus BC31
B8 (U33/U34) FM_A26 Address Bus BC31
F2 (U33) FM_D0 Data Bus AV33
E2 (U33) FM_D1 Data Bus BC33
G3 (U33) FM_D2 Data Bus BD33
E4 (U33) FM_D3 Data Bus BJ33
E5 (U33) FM_D4 Data Bus BF35
G5 (U33) FM_D5 Data Bus AT32
G6 (U33) FM_D6 Data Bus BB34
H7 (U33) FM_D7 Data Bus BD34
E1 (U33) FM_D8 Data Bus AU33
E3 (U33) FM_D9 Data Bus AY34
F3 (U33) FM_D10 Data Bus BB35
F4 (U33) FM_D11 Data Bus BD35
F5 (U33) FM_D12 Data Bus BA34
H5 (U33) FM_D13 Data Bus BB33
G7 (U33) FM_D14 Data Bus AV32
E7 (U33) FM_D15 Data Bus BF34
F2 (U34) FM_D16 Data Bus AW35
E2 (U34) FM_D17 Data Bus BF36
G3 (U34) FM_D18 Data Bus AW34
E4 (U34) FM_D19 Data Bus BG34
E5 (U34) FM_D20 Data Bus BG35
G5 (U34) FM_D21 Data Bus BA36
G6 (U34) FM_D22 Data Bus AT34
H7 (U34) FM_D23 Data Bus AR32
E1 (U34) FM_D24 Data Bus AU32
E3 (U34) FM_D25 Data Bus BJ34
F3 (U34) FM_D26 Data Bus BH35
F4 (U34) FM_D27 Data Bus AV35
F5 (U34) FM_D28 Data Bus AY36
H5 (U34) FM_D29 Data Bus AU35
G7 (U34) FM_D30 Data Bus AR31
E7 (U34) FM_D31 Data Bus AT35
E6 (U33/U44) FLASH_CLK Clock BB29
D4 (U33/U34) FLASH_RESETn Reset BF32
B4 (U33) FLASH_CEn0 Chip Enable 0 BE32
B4 (U34) FLASH_CEn1 Chip Enable 1 BF30
F8 (U33/U34) FLASH_OEn Output Enable BC30
G8 (U33/U34) FLASH_WEn Write Enable BE36
F6 (U33/U34) FLASH_ADVn Address Valid BD30
C6 (U33/U34) FLASH_WPn Write Protect N/A
F7 (U33) FLASH_RDYBSYn0 Ready/Busy BJ31
F7 (U34) FLASH_RDYBSYn1 Ready/Busy AT29

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