Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.7.2. User-Defined DIP Switch

Board reference SW4 and SW5 are two 4-pin DIP switches. The switches are user-defined and are provides additional FPGA input control. When the switch is in the OPEN position, a logic 1 is selected. When the switch is in the CLOSED or ON position, a logic 0 is selected. There is no board-specific function for these switches.

The table below lists the schematic signal names of each DIP switch and their corresponding Intel® Stratix® 10 GX FPGA pin numbers.

Table 11.  User-Defined Switches
Board Reference Schematic Signal Name Intel® Stratix® 10 GX Device Pin Number
SW5.4 USER_DIP0 AV20
SW5.3 USER_DIP1 AV21
SW5.2 USER_DIP2 AT19
SW5.1 USER_DIP3 BE19
SW4.4 USER_DIP4 BB18
SW4.3 USER_DIP5 BC18
SW4.2 USER_DIP6 BD18
SW4.1 S10_UNLOCK BG18

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