Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.4. FPGA Configuration

This section describes the FPGA, flash memory and MAX® V CPLD System Controller device programming methods supported by the Intel® Stratix® 10 GX Transceiver Signal Integrity development kit.
Three configuration methods except AS mode are mostly used on the Intel® Stratix® 10 transceiver signal integrity development kit.
  • Embedded Intel® FPGA Download Cable II is the default method for configuring the FPGA at any time using the Intel® Quartus® Prime Programmer in JTAG mode with the supplied USB cable.
  • MAX® V configures the FPGA device via AvST mode using stored images from CFI flash devices either at power-up or pressing the MAX_RESETn/PGM_CONFIG push button.
  • JTAG external header for debugging. Intel recommends that you use lower JTAG clock frequency value such as 16 MHz.

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