Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

4.1. Board Overview

This section provides an overview of the Intel® Stratix® 10 GX transceiver signal integrity development board including a block diagram of the board.
Figure 2. Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide Block Diagram
Figure 3.  Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit Picture

Intel® Stratix® 10 GX Transceiver Signal Integrity Development Board Components

Table 4.  Board Components Table
Board Reference Type Description
Featured Devices
U43 FPGA

Intel® Stratix® 10 GX 280 F2397 FPGA

U20 CPLD

System MAX® V CPLD (5M2210ZF256)

U97 FPGA

USB Intel® MAX® 10 FPGA (10M04SCU169)

U98 FPGA

PWR Intel® MAX® 10 FPGA (10M16SAU169)

General User Input and Output
D12-D19 User LEDs (Green)

User LEDs (Green)
D20-D25 MAX V LEDs (Green)

MAX® V LEDs (Green)

S2-S13 User Push Buttons

User Push Buttons
SW4-SW5 User DIP Switches

User DIP
SW6 MAX V DIP Switch

MAX® V DIP Switch

J20 LCD Display Header

Connector for 16 Character x2 line LCD
Configuration, Status and Setup Elements
J14 Intel® FPGA Download Cable Programming Header

Header to interface external Intel® FPGA Download Cable direct to FPGA (through USB Intel® MAX® 10)

D1-D2 Green LEDs

JTAG Transmit-Receive Activity
D3-D4 Green LEDs

System Console Transmit-Receive Activity
D36 Amber LEDs

System Power error indicator
D5-D6 Green LEDs

FMC cards present indicator
D7-D11 Ethernet LEDs

Ethernet LEDs (TX/RX/LINK)
Clock Circuits
X2 50-MHz Oscillator

This 50-MHz oscillator is the clock source to clock buffer SL18860DC that provides three 50 MHz outputs to the FPGA and the MAX® V CPLD

X1

This 50-MHz oscillator provides clock to the PWR Intel® MAX® 10 FPGA

SW1 Spread Spectrum/Frequency Selection Switch

SW1 selects frequency and spread spectrum percentages of clock buffer outputs ICS557-03.

Y1 Transceiver Dedicated Reference Clock/Programmable Oscillator

Feeds REFCLKs on left side of the Intel® Stratix® 10 GX FPGA device and an LVDS trigger output at board reference J4/J5.

The external input is available at board reference J2 and J3. The default frequency is 644.53125 MHz.

Y2

Feeds REFCLKs on right side of the Intel® Stratix® 10 GX FPGA device and an LVDS trigger output at board reference J8/J9.

The external input is available at board reference J6 and J7. The default frequency is 706.25 MHz.

U3, U4, U5 Transceiver Dedicated Reference Clock/ Programmable PLL

Feeds REFCLKs on left side of the Intel® Stratix® 10 GX FPGA device and an LVDS trigger output at board reference J10/J11.

The default frequencies are 625 MHz, 614.4 MHz, 100 MHz.

U6

Feeds REFCLKs on right side of the Intel® Stratix® 10 GX FPGA device and an LVDS trigger output at board reference J12/J13.

The default frequencies are 625 MHz, 644.53125 MHz, 125 MHz.

J61, J63 External core clock input

SMA external input at CLKIN_3C0

J62, J64 External core clock output

SMA external output at PLL_3C_CLKOUT0

J65-J66 External transceiver clock input

SMA external input bank at 1C
J67-J68

SMA external input bank at 1M
J69-J70

SMA external input bank at 4C
J71-J72

SMA external input bank at 4K
X4 100-MHz Oscillator

This 100-MHz oscillator provides clock to the MAX® V CPLD

Transceiver Interfaces
J33, J44, J50 MXP connector

17 Gbps/28 Gbps, 4 channels MXP connectors

J31-J32

J34-J43

J45-J49

J51-J57

 2.4 mm RF connector

17 Gbps/ 28 Gbps, 6 channels 2.4 mm RF connectors

J29-J30 SFP+ optical transceiver interface

17 Gbps/28 Gbps, 2 channels connected to SFP+ modules

J27-J28 QSFP28 optical transceiver interface

17 Gbps/28 Gbps, 8 channels connected to QSFP28 modules

J24 CFP4 optical transceiver interface

17 Gbps/ 28 Gbps, 4 channels connected to CFP4 module

J58-J59 FMC+ connector

17 Gbps/28 Gbps, 34 channels connected to FMC+ connectors

Memory Devices
U21-U22 Flash Memory Two 1-Gbit Micron PC28F00AP30BF CFI Flash device
Communication Ports
J19 Gigabit Ethernet Port RJ-45 connector which provides a 10/100/1000 Ethernet connection through a Marvell 88E1111 PHY
CN1 USB Type-B connector Connects a type-B USB cable
Power Supply
U15 LTM2987

Linear Technology power monitor device

U63-U64

U66-U67

LTM4677

3x LTM4650

Power regulators for VCC rail

U68 LTM4620

Power regulators for VCCERAM rail

U69 LTM4620

Power regulators for VCCH rail

U70 LTM4620

Power regulators for VCCRL rail

U71 LTM4620

Power regulators for VCCRR rail

U74 EN63A0

Power regulators for FMCA_VADJ rail

U78 EN63A0

Power regulators for FMCB_VADJ rail

U79 EN6337

Power regulators for 2.5V rail

U82 LTM4630A

Power regulators for 3.3V rail

Level Two Title