Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.10. Communication Ports

The Intel® Stratix® 10 GX transceiver signal integrity development board supports a 10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the Intel® Triple-Speed Ethernet Megacore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA.

The Intel® Stratix® 10 GX FPGA device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function is provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5 V and 1.2 V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 connector with internal magnetics that are used for driving copper lines with Ethernet traffic.

Table 21.  Ethernet PHY Pin Assignments
Schematic Signal Name Marvell 88E1111 (U23) PHY Pin Number Description
ENET_LED_LINK1000 60/73 1000 Mb link LED
ENET_LED_LINK100 74 100 Mb link LED
ENET_LED_LINK10 59/76 10 Mb link LED
ENET_LED_TX 68 TX data active LED
ENET_LED_RX 69 RX data active LED
ENET_SGMII_TX_P 82 SGMII transmit
ENET_SGMII_TX_N 81 SGMII transmit
ENET_SGMII_RX_P 77 SGMII receive
ENET_SGMII_RX_N 75 SGMII receive
ENET_XTAL_25MHZ 55 25 MHz clock
ENET_T_INTn 23 Management bus interrrupt
ENET_RSET 30 Device reset
MDIO_T 24 Management bus data input/output
MDC_T 25 Management bus data clock
MDI_P0 29 Management bus data
MDI_N0 31 Management bus data
MDI_P1 33 Management bus data
MDI_N1 34 Management bus data
MDI_P2 39 Management bus data
MDI_N2 41 Management bus data
MDI_P3 42 Management bus data
MDI_N3 43 Management bus data

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