Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Document Revision History for the Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus® Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Document Revision History for the Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

5.2. Power Supply

Power supply for this development kit is provided through an external laptop style DC power brick connected to a 6-pin ATX power connector. The input voltage is in the range of 12V +/- 5%. This DC voltage is then stepped down to the various power rails used by the components on the development board.

Important: The power rails on the development board have the option to be supplied from an external source through a banana jack or power terminal connectors by first disabling corresponding power regulator using SW9/S14 DIP Switch.
Table 24.  Power per Device on the Development Board
Device Voltage Name Voltage Value (Volts) Note

Stratix® 10 GX FPGA

The device can either be 1SG280LU2F50E2VG (L-Tile version) or 1SG280HU2F50E2VG (H-Tile version).

 S10_VCC 0.85/VID Core and periphery power
S10_VCCRL 1.12/1.03 Left XCVR RX path
S10_VCCRR 1.12/1.03 Right XCVR RX path
S10_VCCT 1.12/1.03 XCVR TX path
S10_VCCERAM 0.9 Memory and PLL digital power
S10_VCCH 1.8 XCVR and PLL analog power
1.8V 1.8 I/O voltage and I/O pre-drivers
2.4V 2.4 VCCFUSEWR power
FMCA_VADJ 1.8/1.5/1.35/1.2 I/O Voltage
FMCB_VADJ 1.8/1.5/1.35/1.2 I/O Voltage
USB MAX® 10 (10M04SCU169) 3.3V_PRE 3.3

Core, PLL and VCCIO

VCCIO for Stratix® 10 Interface
1.8V_PRE 1.8
PWR MAX® 10 (10M16SAU169) 3.3V_STBY 3.3 Altera® Power Management Chip
MAX® V (EPM2210F256) 1.8V 1.8 System Controller
Flash (PC28F00AP30BFx2) 1.8V 1.8 CFI Flash
USB PHY (CY7C68103) 3.3V_PRE 3.3 USB PHY
Ethernet PHY (88E1111) 2.5V 2.5 Ethernet PHY
Power Monitor (LTM2987) 12V_IN 12 Linear Tech Power Management Chip
Clock Buffer (SL18860DC) 1.8V 1.8 Core Clock Buffer
SS Clock Generator (ICS557) 3.3V 3.3 Spread Spectrum / Clock Select capability to core clock

Programmable Oscillator (Si570x2)

Clock Buffer (Si533311x2)

 2.5V 2.5 Transceiver Reference Clock Buffers
Programmable PLL (Si5341x2) 1.8V 1.8 Transceiver Reference Clock and Core Clock
3.3V 3.3
Power Measurement (LTC2418) 5V 5 Measure current in Altera® power management solution
DAC (DAC7578) 3.3V_STBY 3.3 Trim voltage in Altera® power management solution
CFP4 Module 3.3V 3.3 CFP4 Module
QSFP28 Modules 3.3V 3.3 QSFP28 Modules
SFP+ Modules 3.3V 3.3 SFP+ Modules
Level Two Title