Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.3. MAX V CPLD System Controller

The Intel® Stratix® 10 GX transceiver signal integrity development kit consists of a MAX® V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX® V CPLD devices provide programmable solutions for applications such as FPGA reconfiguration from flash memory, I2C chain to manage power consumption, core temperature, fan speed, clock frequency and remote update system. MAX® V devices feature on-chip flash storage, internal oscillator and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX® V CPLDs can help you meet your low power design requirements.

The following list summarizes the features of MAX® V CPLD devices:
  • 2210 Logic Elements (LEs)
  • 8192 bits of User Flash Memory
  • 4 global clocks
  • 1 internal oscillator
  • 271 maximum user I/O pins
  • Low-cost, low power and non-volatile CPLD architecture
  • Fast propagation delays and clock-to-output times
  • Single 1.8V external supply for device core
  • Bus-friendly architecture including programmable slew rate, drive strength, bus-hold and programmable pull-up resistors

The table below lists the MAX® V CPLD I/O signals.

Table 7.  MAX V CPLD I/O Signals
Signal Name Description
FA_A[26:1] Flash Address Bus
FM_D[31:0] Flash Data Bus
FLASH_CLK Flash Clock
FLASH_RESETn Flash Reset
FLASH_CEn[1:0] Flash Chip Enable
FLASH_OEn Flash Output Enable
FLASH_WEn Flash Write Enable
FLASH_ADVn Flash Address Valid
FLASH_RDYBSYn[1:0] Flash Chip Ready/Busy
FPGA_CONFIG_D[31:0] FPGA AvST configuration data bus
FPGA_INIT_DONE FPGA initialization complete
FPGA_nSTATUS FPGA status
FPGA_CONF_DONE FPGA configuration complete
FPGA_nCONFIG FPGA configuration control pin reset to FPGA
FPGA_ASCLK FPGA AS configuration clock
FPGA_SEU_ERR FPGA configuration SEU error
FPGA_CvP_DONE FPGA CvP configuration done
FPGA_SDM FPGA SDM IO10
FPGA_PR_REQUEST FPGA partial reconfiguration request
FPGA_PR_DONE FPGA partial reconfiguration done
FPGA_PR_ERROR FPGA partial reconfiguration error
FPGA_MSEL[2:0] FPGA configuration mode setting bits
FPGA_AVST_CLK FPGA AvST configuration clock
FPGA_AVST_VALID FPGA AvST configuration data valid
FPGA_AVST_READY FPGA ready to receive data
I2C_1V8_SCL MAX V I2C bus
I2C_1V8_SDA MAX V I2C bus
FAPRSNT1V8_N FMC A present indicator
FBPRSNT1V8_N FMC B present indicator
SI5341_1_ENn SI5341 1 ENABLE
SI5341_1_INTn SI5341 1 interrupt indicators
SI5341_1_RSTn SI5341 1 reset
SI5341_1_LOLn SI5341 1 loss of clock indicators
SI5341_2_ENn SI5341 2 ENABLE
SI5341_2_INTn SI5341 2 interrupt indicators
SI5341_2_RSTn SI5341 2 reset
SI5341_2_LOLn SI5341 2 loss of clock indicators
EN_MASTER[1:0] ENABLE specific I2C buffer
TEMP_ALERTn FPGA temperature alert input
OVERTEMPn FPGA over temperature input
OVERTEMP Over temperature fan control
FAN_RPM Fan speed control
USB_CFG[14:0] Bus between USB Intel® MAX® 10 and MAX® V
USB_MAX5_CLK Clock from USB PHY chip
MAX_OSC_CLK_1 25MHz / 100 MHz / 125 MHz clock input
MAX5_JTAG_TCK MAX® V Test Clock
MAX5_JTAG_TMS MAX® V Test Mode Select
MAX5_JTAG_TDI MAX® V Test Data Input
MAX5_JTAG_TDO MAX® V Test Data Output
FACTORY_LOAD Factory image for configuration
MAX5_SWITCH [2:0] System MAX® V user DIP switch
PGM_SEL Flash Memory program select pushbutton
PGM_CONFIG Flash Memory program configuration pushbutton
MAX_RESETn System MAX® V reset pushbutton
CPU_RESETn CPU reset pushbutton
PGM_LED[2:0] Flash image program select indicators
MAXV_ERROR

Intel® Stratix® 10 configuration error indicator LED

MAXV_LOAD

Intel® Stratix® 10 configuration active indicator LED

MAXV_CONF_DONE

Intel® Stratix® 10 configuration done indicator LED

MAX5_BE_n[3:0]

Intel® Stratix® 10 and MAX® V data path, byte enable

MAX5_OEn

Intel® Stratix® 10 and MAX® V data path, output enable

MAX5_CSn

Intel® Stratix® 10 and MAX® V data path, chip select

MAX5_WEn

Intel® Stratix® 10 and MAX® V data path, write enable

MAX5_CLK

Intel® Stratix® 10 and MAX® V data path, clock

SPARE[20:1] Spare bus between MAX® V and Intel® Stratix® 10
CLK_50M_MAX5 50 MHz clock input
FPGA_ASDATA[3:0] Intel® Stratix® 10 AS configuration data
CLK_CONFIG 100 MHz clock input
Figure 4. I2C Block Diagram

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