6.1. Preparing the Board
Several designs are provided to test the major board features. Each design provides data for one or more tabs in the BTS. The Configure Menu identifies the appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears and allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.
The BTS shares the JTAG bus with other applications like Nios® II debugger and the Signal Tap II Embedded Logic Analyzer. As the Intel® Quartus® Prime Programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applications before attempting to reconfigure the FPGA using the Intel® Quartus® Prime Programmer.
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