3.1. Setting up the Development Board
To prepare and apply power to the board, perform the following steps:
- The Intel® Stratix® 10 GX transceiver signal integrity development kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the Factory Default Switch and Jumper Settings to return the board to its factory settings before proceeding.
- The development kit ships with design examples stored in the flash device. The POWER-ON slide switch (SW7) is provided to turn the board ON or OFF.
CAUTION:When the power cord is plugged into connector J103 of the Intel® Stratix® 10 transceiver signal integrity development kit, 12V_IN and 3.3V_STBY are present on to the board with switch SW7 in the 'OFF' position. These voltages are restricted to a small area of the board. When switch SW7 is placed to 'ON' position, all voltages planes have power at this point.
- Set the POWER-ON switch SW7 to the ON position. When power is supplied to the board, three green LEDs (D29, D31 and D32) illuminate and an amber LED (D36) extinguishes indicating that the board has power. If the amber LED (D36) illuminates, it indicates that one or more power supply is incorrect.
- RESET button (S12) is connected to the MAX® V CPLD (MAX_RESETn pin) that is used for AvST configuration. When this button is pressed, the MAX® V CPLD initiates a reloading of the stored image from the flash memory using AvST configuration mode. The image loaded right after power cycle or MAX® V reset depends on FACTORY_LOAD settings.
CAUTION:Use only the supplied power supply. Power regulation circuits on the board can get damaged by power supplies with greater voltage.
- OFF(1) - factory load
- ON (0) - user defined load #1
The MAX® V CPLD device on the board contains a parallel flash loader II (PFL II) megafunction. After a POWER-ON or RESET (reconfiguration) event, the MAX® V CPLD configures the Intel® Stratix® 10 FPGA in AvST mode with either factory design or user design depending on the setting of FACTORY_LOAD.
The development kit includes a MAX® V CPLD design which contains the PFL II megafunction. The design resides in the <package dir>\examples\max5 directory. When configuration is complete, LED D25 (CONF_DONE) illumintes signaling that the Intel® Stratix® 10 GX FPGA device is configured successfully. If the configuration fails, the LED D23 (ERROR) illuminates.