Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

3.1. Setting up the Development Board

To prepare and apply power to the board, perform the following steps:

  1. The Intel® Stratix® 10 GX transceiver signal integrity development kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the Factory Default Switch and Jumper Settings to return the board to its factory settings before proceeding.
  2. The development kit ships with design examples stored in the flash device. The POWER-ON slide switch (SW7) is provided to turn the board ON or OFF.
    CAUTION:
    When the power cord is plugged into connector J103 of the Intel® Stratix® 10 transceiver signal integrity development kit, 12V_IN and 3.3V_STBY are present on to the board with switch SW7 in the 'OFF' position. These voltages are restricted to a small area of the board. When switch SW7 is placed to 'ON' position, all voltages planes have power at this point.
  3. Set the POWER-ON switch SW7 to the ON position. When power is supplied to the board, three green LEDs (D29, D31 and D32) illuminate and an amber LED (D36) extinguishes indicating that the board has power. If the amber LED (D36) illuminates, it indicates that one or more power supply is incorrect.
  4. RESET button (S12) is connected to the MAX® V CPLD (MAX_RESETn pin) that is used for AvST configuration. When this button is pressed, the MAX® V CPLD initiates a reloading of the stored image from the flash memory using AvST configuration mode. The image loaded right after power cycle or MAX® V reset depends on FACTORY_LOAD settings.
    • OFF(1) - factory load
    • ON (0) - user defined load #1
    Page selection can be changed by the PGMSEL button (S10) when the board is powered on, and PGM_CONFIG (S11) is used to reconfigure FPGA with corresponding page which is indicated by PGM_LED0, PGM_LED1 or PGM_LED2.
    CAUTION:
    Use only the supplied power supply. Power regulation circuits on the board can get damaged by power supplies with greater voltage.

The MAX® V CPLD device on the board contains a parallel flash loader II (PFL II) megafunction. After a POWER-ON or RESET (reconfiguration) event, the MAX® V CPLD configures the Intel® Stratix® 10 FPGA in AvST mode with either factory design or user design depending on the setting of FACTORY_LOAD.

The development kit includes a MAX® V CPLD design which contains the PFL II megafunction. The design resides in the <package dir>\examples\max5 directory. When configuration is complete, LED D25 (CONF_DONE) illumintes signaling that the Intel® Stratix® 10 GX FPGA device is configured successfully. If the configuration fails, the LED D23 (ERROR) illuminates.

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