Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.4.2. FPGA Programming from Flash Memory

The figure below shows a detailed schematic block diagram for the MAX V + Flash AvSTx32 mode configuration implementation.

Note: Typical JTAG clock frequency for CFI Flash programming via PFL II core is 16 MHz. You may try it with a lower frequency such as 6 MHz if it fails with 16 MHz.
Figure 6. MAX V + Flash AvSTx32 Configuration Block Diagram

Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its Flash interface signals to avoid contention with the FPGA. The PGMSEL dipswitch (S10) is provided to select between two POF files (FACTORY and USER) stored on the Flash.

The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx32 configuration in the MAX® V CPLD. The PFL II Megafunction reads data from the flash and converts it to AvST format. This data is written into the Intel® Stratix® 10 GX FPGA device through dedicated AvST CLK and FPGA Config Data [31:0] pins at corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.

Implementation will be done using an Intel® MAX® V 5M2210ZF256FBGA CPLD acting as the AvST download controller and two 1G Flash devices. The Flash will be Numonyx 1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX® V CPLD shares the CFI Flash interface with the Intel® Stratix® 10 GX FPGA. No arbitration is needed between MAX® V CPLD and Intel® Stratix® 10 GX FPGA to access the Flash as the CPLD only has access prior to FPGA initialization.

After a POWER-ON or RESET (reconfiguration) event, the MAX® V device shall configure the Intel® Stratix® 10 GX FPGA in the AvSTx32 mode with either the FACTORY POF or an USER DEFINED POF depnding on the FACTORY_LOAD setting.

The MSEL[2:0] pins indicate which configuration scheme is chosen. The manufacturing default condition is [000] for AvSTx32 scheme.

For different configuration modes, MSEL [2:0] signals must be set acccording to the table below:
Table 8.  Support Configuration Modes for Stratix 10 Transceiver Signal Integrity Development Kit
Configuration Scheme MSEL [2:0]
Avalon-ST (x32) 000
Avalon-ST (x16) 101
AS (Normal mode) 011
JTAG only 111
Not supported Other Settings

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