Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Document Revision History for the Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus® Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Document Revision History for the Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

5.3. Power Management

Two power management solutions are provided in the Stratix® 10 GX Transceiver Signal Integrity Development Kit:
  • Linear Tech LTM2987
  • Altera® power MAX® 10 logic

You can select either of the aforementioned power management solutions by using Sw8-3.

LTM2987 or power MAX® 10 devices are capable of measuring the voltage, measuring the current, trimming the voltage and sequencing the order at power on and power off. Voltages can be trimmed upto +/- 10%. Communication to these devices is through I2C interface. A Linear Technology power monitor application known as LTPowerPlay is utilized to measure, trim and observe each voltage rail's condition.

Table 25.  Functions supported by the two Power Management Solutions
Rail Name LT/ Altera® Voltage Monitor LT/ Altera® Current Monitor LT Voltage Trim Altera® Voltage Trim LT/ Altera® PWR Sequence Control
VCC Y - - - Y
VCCRL Y Y Y N* Y
VCCRR Y Y Y N* Y
VCCT Y Y Y N* Y
VCCH Y Y Y N* Y
VCCERAM Y Y Y N* Y
1.8V Y Y Y N* Y
3.3V Y N N N Y
2.5V Y N N N Y
12V Y N - - Y
Note: *: Default not supported, request for an example design if you want this feature.
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