Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.4.3. FPGA Programming over External Intel® FPGA Download Cable II

The JTAG chain allows programming of both the Intel® Stratix® 10 GX FPGA and MAX® V CPLD devices using an external Intel® FPGA Download Cable II dongle or the on-board Intel® FPGA Download Cable II via the USB Interface Connector.

During board bring-up, and as a back-up in case the on-board Intel® FPGA Download Cable II has a problem, the external Intel® FPGA Download Cable II dongle can be used to program both the Intel® Stratix® 10 and MAX® V CPLD via the Intel® FPGA Download Cable II 2x5 pin 0.1" programming header (J14)

Another 2x5 pin 0.1" vertical non-shrouded header (J15) is provided on the board for programming the Intel® MAX® 10 FPGA for configuring the Intel® FPGA Download Cable II circuitry. Once the Intel® FPGA Download Cable II is configured and operational, the Intel® FPGA Download Cable II can be used for subsequent programming of the Intel® Stratix® 10 GX FPGA and MAX® V CPLD.

The Intel® FPGA Download Cable II JTAG chain connects four JTAG nodes in the following order, with the option to bypass the Intel® Stratix® 10, MAX® V, FMC A or FMC B by a dip switch SW3 setting as follows:
  • Switch closed/ON: Corresponding JTAG node is bypassed.
  • Switch open/OFF: Corresponding JTAG node is enabled in the JTAG chain.

Pin 2 of the J14 Header is used to disable the embedded Intel® FPGA Download Cable II by connecting it to the embedded Intel® FPGA Download Cable IIs low active disable pin with a pull-up resistor. Since Pin 2 from the mating Intel® FPGA Download Cable II dongle is GND, when the dongle is connected into the JTAG header, the embedded Intel® FPGA Download Cable II is disabled to avoid contention with the external Intel® FPGA Download Cable II dongle.

Figure 7. JTAG Chain

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