Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.8.1. Transceiver Dedicated Clocks

Dedicated clocking scheme that is implemented on the Intel® Stratix® 10 GX transceiver signal integrity development board allows four different protocols to run simultaneously by the Intel® Stratix® 10 GX FPGA.

Four differential clock sources are provided from an I2C programmable VCO oscillator or PLL to the dedicated REFCLK input pins of transceiver blocks on both sides of the FPGA. The default frequencies for these two oscillators and PLLs at startup are:
  • 644.53125 MHz (Y1 left side xcvrs and U6 right side xcvrs)
  • 706.25 MHz (Y2 right side xcvrs)
  • 625 MHz (U5 left side xcvrs and U6 right side xcvrs)
  • 614.4 MHz (U5 left side xcvrs)

The default frequencies can be overridden and a different frequency can be programmed into the oscillators and PLLs for support of other protocols.

Note: Programmed frequencies are lost upon a board power down. Oscillator and PLL frequencies return to their default frequency upon power up.

Each oscillator or PLL provides a differential LVDS trigger output to SMA connectors for scope or other lab equipment triggering purposes.

In addition to the two oscillators and PLLs, each sides have two dedicated differential REFCLK input from a pair of SMA connectors to allow use of lab equipment clock generators as the transceiver clock source.

The four inputs below connect directly to the transceiver clock inputs:
  • J65/J66 SMA connectors direct connection to REFCLK_GXB1C block
  • J67/J68 SMA connectors direct connection to REFCLK_GXB1M block
  • J69/J70 SMA connectors direct connection to REFCLK_GXB4C block
  • J71/J72 SMA connectors direct connection to REFCLK_GXB4K block

The figure below shows the dedicated transceiver clocks that are implemented on the Intel® Stratix® 10 GX FPGA development kit.

Figure 8. Transceiver Dedicated Clocks

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