Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

ID 683206
Date 7/24/2019
Public
Document Table of Contents

4.8.2. General-Purpose Clocks

In addtion to transceiver dedicated clocks, five other clock sources are provided to the FPGA Global CLK inputs for general FPGA design as shown in the figure below.

The usage of these clocks is as follows:
  • 50 MHz oscillator through an SL18860 buffer for Nios® II applications. USB_FPGA_CLK drives from on-board Intel® FPGA Download Cable circuit.
  • 25 MHz crystal supplied to an ICS557-03 Spread Spectrum differential clock buffer. The available frequencies and down spread percentages available from the spread spectrum buffer as shown in the table below.
  • External differential clock source from SMA connectors. Dedicated differential output clock to SMA connectors.
  • Three clock outputs are provided from two Si5341 PLLs:
    • CLK_S10_BOT_100M: 100 MHz LVDS standard
    • CLK_S10_TOP_125M: 125 MHz LVDS standard
    • FPGA_OSC_CLK_1: 125 MHz 1.8V CMOS standard
  • Another clock source is clock from FMC daughter cards.
Figure 9. FPGA Clocks
Table 14.  Spread Spectrum Clock Settings and Frequencies
Spread Spectrum Buffer (Inputs) Output Clock Select (MHz) Spread (%)
SS1/S1 SS0/S0  
0 0 25 (Default) Center+/-0.25
0 1 100 Down -0.5
1 0 125 Down -0.75
1 1 200 No Spread

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