4.8.2. General-Purpose Clocks
In addtion to transceiver dedicated clocks, five other clock sources are provided to the FPGA Global CLK inputs for general FPGA design as shown in the figure below.
- 50 MHz oscillator through an SL18860 buffer for Nios® II applications. USB_FPGA_CLK drives from on-board Intel® FPGA Download Cable circuit.
- 25 MHz crystal supplied to an ICS557-03 Spread Spectrum differential clock buffer. The available frequencies and down spread percentages available from the spread spectrum buffer as shown in the table below.
- External differential clock source from SMA connectors. Dedicated differential output clock to SMA connectors.
- Three clock outputs are provided from two Si5341 PLLs:
- CLK_S10_BOT_100M: 100 MHz LVDS standard
- CLK_S10_TOP_125M: 125 MHz LVDS standard
- FPGA_OSC_CLK_1: 125 MHz 1.8V CMOS standard
- Another clock source is clock from FMC daughter cards.
|Spread Spectrum Buffer (Inputs)||Output Clock Select (MHz)||Spread (%)|
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