L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 9/12/2024
Public
Document Table of Contents

6.1.6. TX Credit Interface

Before a TLP can be transmitted, flow control logic verifies that the link partner's RX port has sufficient buffer space to accept it. The TX Credit interface reports the link partner's available RX buffer space to the Application. It reports the space available in units called Flow Control credits.

Flow Control credits are defined for the following TLP categories:

  • Posted transactions - TLPs that do not require a response
  • Non-Posted transactions - TLPs that require a completion
  • Completions - TLPs that respond to non-posted transactions
Table 35.  Categorization of Transactions Types
TLP Type Category
Memory Write Posted

Memory Read

Memory Read Lock

Non-posted

I/O Read

I/O Write

Non-posted

Configuration Read

Configuration Write

Non-posted
Message Posted

Completions

Completions with Data

Completion Locked

Completion Lock with Data

Completions
Fetch and Add AtomicOp Non-posted
Table 36.  Flow Control CreditsThe following table translates flow control credits to dwords. The PCI Express Base Specification defines a dword as four bytes.
Credit Type Number of Dwords
Header credit - completions 4 dwords
Header credit - requests 5 dwords
Data credits 4 dwords
Table 37.  TX Flow Control Credit InterfaceThe IP core provides TX credit information to the Application Layer. To optimize performance, the Application can perform credit-based checking before submitting requests for transmission, and reorder packets to improve throughput. The IP core always checks for sufficient TX credits before transmitting any TLP.

Signal

Direction

Description

tx_ph_cdts[7:0]

Output

Header credit net value for the flow control (FC) posted requests.
tx_pd_cdts[11:0]

Output

Data credit net value for the FC posted requests.
tx_nph_cdts[7:0]

Output

Header credit net value for the FC non-posted requests.

tx_npd_cdts[11:0] L-Tile

Output

Data credit net value for the FC non-posted requests.

The tx_npd_cdts[11:0] is not available for H-Tile devices. You can monitor the non-posted header credits to determine if there is sufficient space to transmit the next non-posted data TLP.

tx_cplh_cdts[7:0]

Output

Header credit net value for the FC Completion. A value of 0xFF indicates infinite Completion header credits.
tx_cpld_cdts[11:0]L-Tile

Output

Data credit net value for the FC Completion. A value of 0xFF indicates infinite Completion data credit.

The tx_cpld_cdts[11:0] is not available for H-Tile devices. You can monitor the completion header credits to determine if there is sufficient space to transmit the next non-posted data TLP. The completion TLP size is either the request data size or 64 bytes when the completion is split.

For Root Ports or non peer-to-peer Endpoints as the link partner, assume that this credit is infinite.

tx_hdr_cdts_consumed[1:0]

Output

Asserted for 1 coreclkout_hip cycle, for each header credit consumed by the application layer traffic. Note that credits the Hard IP consumes for internally generated Completions or Messages are not tracked in this signal.

For the Gen3 x16 512-bit interface, tx_hdr_cdts_consumed[1] is for the higher bus and tx_hdr_cdts_consumed[0] is for the lower bus.

There is only one tx_hdr_cdts_consumed signal for the 256-bit interface.

tx_data_cdts_consumed[1:0]

Output

Asserted for 1 coreclkout_hip cycle, for each data credit consumed. Note that credits the Hard IP consumes for internally generated Completions or Messages are not tracked in this signal.

For the Gen3 x16 512-bit interface, tx_data_cdts_consumed[1] is for the higher bus and tx_data_cdts_consumed[0] is for the lower bus.

There is only one tx_data_cdts_consumed signal for the 256-bit interface.

tx_cdts_type[<n>-1:0] Output

Specifies the credit type shown on the tx_cdts_data_value[1:0] bus. The following encodings are defined:

  • 2'b00: Posted credits

  • 2'b01: Non-posted credits3

  • 2'b10: Completion credits

  • 2'b11: Reserved

For the Gen3 x16 512-bit interface, tx_cdts_type[3:2] is for the higher bus and tx_cdts_type[1:0] is for the lower bus.

tx_cdts_data_value[3:0] L-Tile, 16 lanes

tx_cdts_data_value[1:0] L-Tile, 8 lanes or fewer

tx_cdts_data_value[1:0] H-Tile, 16 lanes

tx_cdts_data_value H-Tile, 8 lanes or fewer

Output

For H-Tile: 1 = 2 data credits consumed; 0 = 1 data credit consumed.

For L-Tile: The value of tx_cdts_data_value+1 specifies the data credit consumed.

For both H- and L-Tiles: Only valid when tx_data_cdts_consumed asserts.

For the Gen3 x16 512-bit interface, tx_cdts_data_value[1] is for the higher bus and tx_cdts_data_value[0] is for the lower bus.

3 The PCIe IP core does not consume non-posted credits.