L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 9/12/2024
Public
Document Table of Contents

8.1.10.11. TPH Requester Control Register

Table 84.  TPH Requester Control Register - ox1D0

Bits

Register Description

Default Value

Access

[31:9]

Reserved.

0

RO

[8] TPH Requester Enable: When set to 1, the Function can generate requests with Transaction Processing Hints. 0

RW

[7:3] Reserved. 0

RO

[2:0] ST Mode. The following encodings are defined:
  • 3b'000: No Steering Tag Mode
  • 3'b001: Interrupt Vector Mode
  • 3'b010: Device-specific mode
  • 3'b011 - 3'b111: Reserved
0

RW