L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 9/12/2024
Public
Document Table of Contents

9.4.11.2. ebfm_log_stop_sim Verilog HDL Function

The ebfm_log_stop_sim procedure stops the simulation.

Location

altrpcietb_bfm_log.v

Syntax

Verilog HDL: return:=ebfm_log_stop_sim(success);

Argument

success

When set to a 1, this process stops the simulation with a message indicating successful completion. The message is prefixed with SUCCESS.

Otherwise, this process stops the simulation with a message indicating unsuccessful completion. The message is prefixed with FAILURE.

Return

return

Always 0. This value applies only to the Verilog HDL function.