External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public
Document Table of Contents

4.1.6.2. pll_locked for RLDRAM 3

PLL locked signal

Table 153.  Interface: pll_lockedInterface type: Conduit
Port Name Direction Description
pll_locked Output PLL lock signal to indicate whether the PLL has locked