External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public
Document Table of Contents

4.1.3.17. cal_debug_clk for LPDDR3

User calibration debug clock interface

Table 93.  Interface: cal_debug_clkInterface type: Clock Input
Port Name Direction Description
cal_debug_clk Input User clock domain