P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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Document Table of Contents

A.1.5. MSI-X Registers

This section describes the registers previously shown in the MSI-X capability structure.
Table 125.  MSI-X Control Register
Bit Location Description Access Default Value
31

MSI-X Enable: This bit must be set to enable the MSI-X interrupt generation.

You need to obtain this information from the Configuration Intercept Interface.

RW 0
30

MSI-X Function Mask: This bit can be set to mask all MSI-X interrupts from this function.

You need to obtain this information from the Configuration Intercept Interface.

RW 0
29:27 Reserved RO 0
26:16

Size of the MSI-X table (number of MSI-X interrupt vectors). The value in this field is one less than the size of the table set up for this function. Maximum value is 0x7FF (2048 interrupt vectors).

This field is shared among all VFs attached to one PF.

RO Programmed via the programming interface.
15:8 Next Capability Pointer Points to the PCI Express Capability. RO Programmed via the programming interface.
7:0 Capability ID assigned by PCI-SIG. RO 0x11
Table 126.  MSI-X Table Offset Register
Bit Location Description Access Default Value
2:0

BAR Indicator Register: Specifies the BAR corresponding to the memory address range where the MSI-X table of this function is located (000 = VF BAR0, 001 = VF BAR1, …, 101 = VF BAR5).

This field is shared among all VFs attached to one PF.

RO Programmed via the programming interface.
31:3

Offset of the memory address where the MSI-X table is located, relative to the specified BAR. The address is extended by appending three zeroes to make it Qword aligned.

This field is shared among all VFs attached to one PF.

RO Programmed via the programming interface.
Table 127.  MSI-X Pending Bit Array Register
Bit Location Description Access Default Value
2:0

BAR Indicator Register: Specifies the BAR corresponding to the memory address range where the Pending Bit Array of this function is located (000 = VF BAR0, 001 = VF BAR1, …, 101 = VF BAR5).

This field is shared among all VFs attached to one PF.

RO Programmed via the programming interface.
31:3

Offset of the memory address where the Pending Bit Array is located, relative to the specified BAR. The address is extended by appending three zeroes to make it Qword aligned.

This field is shared among all VFs attached to one PF.

RO Programmed via the programming interface.

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