P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.2.2.2. Function-Level Reset (FLR) Interface (EP Only)

FLR allows specific physical/virtual functions to be reset without affecting other physical/virtual functions or the link they share. FLR can be enabled by checking the check-box Enable Function Level Reset (FLR) in the PCIe Device tab of the PCIe PCI Express / PCI Capabilities tab in the GUI.

This interface is only present in EP mode (for x16/x8 configurations).

Table 48.  FLR Interface
Signal Name Direction Description Clock Domain EP/RP/BP
p<n>_flr_rcvd_pf_o[7:0] where n = 0, 1 O

Active high signals. Once asserted, the signals remain high until the Application Layer sets the p<n>_flr_completed_pf_i[7:0] high for the associated function. The Application Layer must perform actions necessary to clear any pending transactions associated with the function being reset.

After the assertion of p<n>_flr_rcvd_pf_o[7:0], the Application Layer must assert p<n>_flr_completed_pf_i[7:0] within 100ms to indicate it has completed the FLR actions and is ready to re-enable the PF.

These busses are differentiated by the prefixes p<n>.

coreclkout_hip EP
p<n>_flr_rcvd_vf_o where n = 0, 1 O

A one-cycle pulse indicates that an FLR was received from host targeting a VF. When port bifurcation is used, there is one such signal for each Avalon-ST interface. These signals are differentiated by the prefixes p<n>.

After the assertion of p<n>_flr_rcvd_vf_o, the Application Layer must assert p<n>_flr_completed_vf_i within 100ms to indicate it has completed the FLR actions and is ready to re-enable the VF.

coreclkout_hip EP
p<n>_flr_rcvd_pf_num_o[2:0] where n = 0, 1 O Parent PF number of the VF undergoing FLR. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p<n>. coreclkout_hip EP
p<n>_flr_rcvd_vf_num_o[10:0] where n = 0, 1 O VF number offset of the VF undergoing FLR. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p<n>. coreclkout_hip EP
p<n>_flr_completed_pf_i[7:0] where n = 0, 1 I One bit per PF. A one-cycle pulse on any bit indicates that the application has completed the FLR sequence for the corresponding PF and is ready to be enabled. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p<n>. coreclkout_hip EP
p<n>_flr_completed_vf_i where n = 0, 1 I

One-cycle pulse from the application re-enables a VF. When port bifurcation is used, there is one such signal for each Avalon-ST interface. These signals are differentiated by the prefixes p<n>.

The minimum separation between two consecutive pulses is four clocks.

coreclkout_hip EP
p<n>_flr_completed_pf_num_i[2:0] where n = 0, 1 I Parent PF number of the VF to re-enable. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p<n>. coreclkout_hip EP
p<n>_flr_completed_vf_num_i[10:0] where n = 0, 1 I VF number offset of the VF to re-enable. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p<n>. coreclkout_hip EP

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