P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1.1. Clock Domains

The P-Tile IP for PCI Express* has three primary clock domains:
  • PHY clock domain (i.e. core_clk domain): this clock is synchronous to the SerDes parallel clock.
  • EMIB/FPGA fabric interface clock domain (i.e. pld_clk domain): this clock is derived from the same reference clock (refclk0) as the one used by the SerDes. However, this clock is generated from a stand-alone core PLL.
  • Application clock domain (coreclkout_hip): this clock is an output from the P-Tile IP, and it has the same frequency as pld_clk.
Figure 2. Clock Domains

The PHY clock domain (i.e. core_clk domain) is a dynamic frequency domain. The PHY clock frequency is dependent on the current link speed.

Table 10.  PHY Clock and Application Clock Frequencies
Link Speed PHY Clock Frequency Application Clock Frequency
Gen1 125 MHz Gen1 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz.
Gen2 250 MHz Gen2 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz.
Gen3 500 MHz 250 MHz
Gen4 1000 MHz

175 MHz / 200 MHz / 225 MHz / 350 MHz / 400 MHz / 450 MHz ( Intel® Stratix® 10 DX)

175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz ( Intel® Agilex™ )

Note: For a link down-training scenario when P-tile is configured at Gen3 or Gen4 and the link gets down-trained to a lower speed, the application clock frequency will continue to run at the configured frequency set in the PLD Clock Frequency parameter. For example, the PCIe Hard IP Mode parameter is set as a Gen4 1x16 and the PLD Clock Frequency parameter as 450 MHz, the PLD clock frequency will continue to run at 450 MHz even if the Link is down-trained to Gen3 or less.

Did you find the information on this page useful?

Characters remaining:

Feedback Message