E.2.1. Avalon® -ST PCIe PIO Example Design
In the Avalon® -ST PCIe IP GUI, configure the Avalon® -ST PCIe IP as a Gen4 x16 Endpoint and generate the example design. This example design automatically creates the files for simulation. Following is the top-level testbench block diagram showing the default Root Port BFM and PIO example design.
For details on the example design generation, refer to the Quick Start Guide chapter of the Intel FPGA P-Tile Avalon® -ST IP for PCI Express User Guide.
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