P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.11. Configuration Intercept Interface (EP Only)

The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior.

The application logic should detect the CFG request at the rising edge of cii_req. Due to the latency of the EMIB, the cii_req can be deasserted many cycles after the deassertion of cii_halt.

The application logic can use the CII to:
  • Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first.
  • Overwrite the data payload of a CfgWr request. The application logic can also overwrite the data payload of a CfgRd completion TLP.

This interface also allows you to implement the Intel Vendor Specific Extended Capability (VSEC) registers. All configuration accesses targeting the Intel VSEC registers (addresses 0xD00 to 0xFFF) are automatically mapped to this interface and can be monitored via this interface.

If you are not using this interface, tie cii_halt_p0/1 to logic 0.

Note:
The following Configuration accesses will not be visible on CII:
  1. Write to the PF AER Capability Uncorrectable Error Mask Register.
  2. Write to the PF AER Capability Uncorrectable Error Severity Register.
  3. Read to the last PF's ARI Capability and Control Register.
  4. Read to the VF's PCIe Capability Link Control and Link Status Register.
  5. Read to the VF's PCIe Capability Device Control 2 and Status 2 Register.
  6. Write to the VF's ATS Requester Capability Register.
The following Configuration accesses will not be visible on CII due to the VirtIO Capability Register implementation in soft logic.
  • All Read/Write accesses to the PF/VF VirtIO Capability register range.
Figure 40. Configuration Intercept Interface Timing Diagram
Table 75.  Configuration Intercept Interface
Signal Name Direction Description Clock domain EP/RP/BP
cii_req_o O

Indicates the CFG request is intercepted and all the other CII signals are valid.

coreclkout_hip EP
cii_hdr_poisoned_o O

The poisoned bit in the received TLP header on the CII.

coreclkout_hip EP
cii_hdr_first_be_o[3:0] O

The first dword byte enable field in the received TLP header on the CII.

coreclkout_hip EP
cii_func_num_o[2:0] O

The function number in the received TLP header on the CII. Applicable when multiple Physical Functions are enabled.

coreclkout_hip EP
cii_wr_vf_active_o O

Indicates that the received Configuration TLP targets a virtual function (VF) inside the controller. This VF is identified by cii_vf_num. Applicable when SR-IOV is enabled.

coreclkout_hip EP
cii_vf_num_o[10:0] O

Identifies the virtual function (VF) inside the controller that was targeted by the Configuration TLP. This signal is valid when cii_wr_vf_active_o is asserted. Applicable when SR-IOV is enabled.

coreclkout_hip EP
cii_wr_o O

Indicates that cii_dout_p0/1 is valid. This signal is asserted only for a configuration write request.

coreclkout_hip EP
cii_addr_o[9:0] O

The double word register address in the received TLP header on the CII.

coreclkout_hip EP
cii_dout_o[31:0] O

Received TLP payload data from the link partner to your application client. The data is in little endian format. The first received payload byte is in [7:0].

coreclkout_hip EP
cii_override_en_i I

Override enable. When the application logic asserts this input, the PCIe Hard IP overrides the CfgWr payload or CfgRd completion using the data supplied by the application logic on cii_override_din.

coreclkout_hip EP
cii_override_din_i[31:0] I
Override data.
  • CfgWr: override the write data to the PCIe Hard IP register with data supplied by the application logic on cii_override_din.
  • CfgRd: override the data payload of the completion TLP with data supplied by the application logic on cii_override_din.
coreclkout_hip EP
cii_halt_i I

Flow control input signal. When cii_halt_p0/1 is asserted, the PCIe Hard IP halts the processing of CFG requests for the PCIe configuration space registers.

coreclkout_hip EP

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