P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.12.2.1. Using Direct User Avalon-MM Interface (Byte Access)

Targeting PF Configuration Space Registers

User application needs to specify the offsets of the targeted PF registers.

For example, if the application wants to read the MSI Capability Register of PF0, it will issue a Read with address 0x0050 to target the MSI Capability Structure of PF0.

Figure 43. PF Configuration Space Registers Access Timing Diagram

Targeting VF Configuration Space Registers

User application needs to first specify the VF number of the targeted configuration register.

The application needs to program the User Avalon-MM Control Register at offset 0x10406A accordingly.

For example, to read VF3's MSI-X Capability registers of Physical Function 0, the user application needs to:
  1. Issue a user Avalon® -MM Write request with address 0x10406A and data 0xE ( vf_num[28:18] = 3, vf _select[17] = 1).
  2. Issue a user Avalon® -MM Read request with address 0xB0 to access VF3 registers of Physical Function 0. In the case of Physical Function 1, the address will be 0x10B0.
Note: You need to reprogram the User Avalon-MM Control Register to access PF registers.
Figure 44. VF Configuration Space Registers Access Timing Diagram

Targeting VSEC Registers

User application needs to program the VSEC field (0x104068 bit[0]) first. Then all accesses from the user Avalon® -MM interface starting at offset 0xD00 will be translated to VSEC configuration space registers.

Figure 45. VSEC Registers Access Timing Diagram

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