P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 )

This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.

Table 33.  VirtIO Device Specific BAR Offset Register
Bit Location Description Access Type Default Value
31:0 BAR Offset RO Settable through Platform Designer

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