P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. TLP Bypass Mode

The P-Tile Avalon® -ST IP for PCIe includes a TLP Bypass mode for both downstream and upstream ports to allow the implementation of advanced features such as:
  • The upstream port or the downstream port of a switch.
  • A custom implementation of a Transaction Layer to meet specific user requirements.
Table 40.  Supported TLP Bypass ConfigurationsUP = upstream port; DN = downstream port
IP Mode Port Mode
X16

UP

DN

X8

UP/UP

UP/DN

DN/UP

DN/DN

X4

UP/UP/UP/UP

DN/DN/DN/DN

Did you find the information on this page useful?

Characters remaining:

Feedback Message