P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.10. Configuration Output Interface

The Transaction Layer configuration output (tl_cfg) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems.

Note: User application logic should not use this interface during TLP Bypass mode as the information on this interface is not valid in that mode.
Table 72.  Configuration Output Interface
Signal Name Direction Description Clock Domain EP/RP/BP
tl_cfg_ctl_o[15:0] O Multiplexed data output from the register specified by tl_cfg_add_o[4:0]. The detailed information for each field in this bus is defined in the following table. coreclkout_hip EP/RP/BP
tl_cfg_add_o[4:0] O This address bus contains the index indicating which Configuration Space register information is being driven onto the tl_cfg_ctl_o[15:0] bits. coreclkout_hip EP/RP/BP

x16/x8: tl_cfg_func_o[2:0]

x4: NA

O Specifies the function whose Configuration Space register values are being driven out on tl_cfg_ctl_o[15:0].
  • 3'b000: Physical Function 0 (PF0)
  • 3'b001: PF1

and so on

coreclkout_hip EP/RP/BP

The table below provides the tl_cfg_add_o[4:0] to tl_cfg_ctl_o[15:0] mapping.

Table 73.  Multiplexed Configuration Information Available on tl_cfg_ctl
tl_cfg_add_o[4:0] tl_cfg_ctl_o[15:8] tl_cfg_ctl_o[7:0]
5'h00

[15]: memory space enable

[14]: IDO completion enable

[13]: perr_en

[12]: serr_en

[11]: fatal_err_rpt_en

[10]: nonfatal_err_rpt_en

[9]: corr_err_rpt_en

[8]: unsupported_req_rpt_en

Device control:

[7]: bus master enable

[6]: extended tag enable

[5:3]: maximum read request size

[2:0]: maximum payload size

5'h01

[15]: IDO request enable

[14]: No Snoop enable

[13]: Relaxed Ordering enable

[12:8]: Device number

bus number
5'h02

[15]: pm_no_soft_rst

[14]: RCB control

[13]: Interrupt Request (IRQ) disable

[12:8]: PCIe Capability IRQ message number

[7:5]: reserved

[4]: system power control

[3:2]: system attention indicator control

[1:0]: system power indicator control

5'h03 Number of VFs [15:0]
5'h04

[15]: reserved

[14]: AtomicOP Egress Block field (cfg_atomic_egress_block)

[13:9]: ATS Smallest Translation Unit (STU)[4:0]

[8]: ATS cache enable

[7]: ARI forward enable

[6]: Atomic request enable

[5:3]: TPH ST mode

[2:1]: TPH enable

[0]: VF enable

5'h05
[15:12]: auto negotiation link speed. Link speed encoding values are:
  • Gen1 : 0x1
  • Gen2 : 0x2
  • Gen3 : 0x4
  • Gen4 : 0x8

[11:1]: Index of Start VF [10:0]

[0]: reserved

 
5'h06 MSI Address [15:0]
5'h07 MSI Address [31:16]
5'h08 MSI Address [47:32]
5'h09 MSI Address [63:48]
5'h0A MSI Mask [15:0]
5'h0B MSI Mask [31:16]
5'h0C

[15]: cfg_send_f_err

[14]: cfg_send_nf_err

[13]: cfg_send_cor_err

[12:8]: AER IRQ message number

[7]: Enable extended message data for MSI (cfg_msi_ext_data_en)

[6]: MSI-X func mask

[5]: MSI-X enable

[4:2]: Multiple MSI enable

[1]: 64-bit MSI

[0]: MSI enable

5'h0D MSI Data [15:0]  
5'h0E AER uncorrectable error mask [15:0]
5'h0F AER uncorrectable error mask [31:16]
5'h10 AER correctable error mask [15:0]
5'h11 AER correctable error mask [31:16]
5'h12 AER uncorrectable error severity [15:0]
5'h13 AER uncorrectable error severity [31:16]
5'h14 [15:8]: ACS Egress Control Register (cfg_acs_egress_ctrl_vec)

[7]: ACS function group enable (cfg_acs_func_grp_en)

[6]: ACS direct translated P2P enable (cfg_acs_p2p_direct_tranl_en)

[5]: ACS P2P egress control enable (cfg_acs_egress_ctrl_en)

[4]: ACS upstream forwarding enable (cfg_acs_up_forward_en)

[3]: ACS P2P completion redirect enable (cfg_acs_p2p_compl_redirect_en)

[2]: ACS P2P request redirect enable (cfg_acs_p2p_req_redirect_en)

[1]: ACS translation blocking enable (cfg_acs_at_blocking_en)

[0]: ACS source validation enable (RP) (cfg_acs_validation_en)

5'h15

[15:13]: reserved

[12]: PRS_RESP_FAILURE (cfg_prs_response_failure)

[11]: PRS_UPRGI (cfg_prs_uprgi)

[10]: PRS_STOPPED (cfg_prs_stopped)

[9]: PRS_RESET (cfg_prs_reset)

[8]: PRS_ENABLE (cfg_prs_enable)

[7:3]: reserved

[2:0]: ARI function group (cfg_ari_func_grp)

5'h16 PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [15:0]  
5'h17 PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [31:16]  
5'h18

[15:10]: reserved

[9]: Disable autonomous generation of LTR clear message (cfg_disable_ltr_clr_msg)

[8]: LTR mechanism enable (cfg_ltr_m_en)

[7]: Infinite credits for Posted header

[6]: Infinite credits for Posted data

[5]: Infinite credits for Completion header

[4]: Infinite credits for Completion data

[3]: End-end TLP prefix blocking (cfg_end2end_tlp_pfx_blck)

[2]: PASID enable (cfg_pf_pasid_en)

[1]: Execute permission enable (cfg_pf_passid_execute_perm_en )

[0]: Privileged mode enable (cfg_pf_passid_priv_mode_en)

5'h19

[15:9]: reserved

[8]: Slot control attention button pressed enable (cfg_atten_button_pressed_en)

[7]: Slot control power fault detect enable (cfg_pwr_fault_det_en)

[6]: Slot control MRL sensor changed enable (cfg_mrl_sensor_chged_en)

[5]: Slot control presence detect changed enable (cfg_pre_det_chged_en)

[4]: Slot control hot plug interrupt enable (cfg_hp_int_en)

[3]: Slot control command completed interrupt enable (cfg_cmd_cpled_int_en)

[2]: Slot control DLL state change enable (cfg_dll_state_change_en)

[1]: Slot control accessed (cfg_hp_slot_ctrl_access)

[0]: PF’s SERR# enable (cfg_br_ctrl_serren)

5'h1A LTR maximum snoop latency register (cfg_ltr_max_latency[15:0])  
5'h1B LTR maximum no-snoop latency register (cfg_ltr_max_latency[31:16])  
5'h1C [15:8]: enabled Traffic Classes (TCs) (cfg_tc_enable[7:0])

[5:0]: auto negotiation link width

6’h01 = x1

6’h02 = x2

6’h04 = x4

6’h08 = x8

6’h10 = x16

5'h1D MSI Data[31:16]
5'h1E N/A
5'h1F N/A
Note:

The information on the Configuration Output (tl_cfg) bus is time-division multiplexed (TDM).

  • When tl_cfg_func[2:0] = 3'b000, tl_cfg_ctl[31:0] drive out the PF0 Configuration Space register values.
  • Then, tl_cfg_func[2:0] are incremented to 3'b001.
  • When tl_cfg_func[2:0] = 3'b001, tl_cfg_ctl[31:0] drive out the PF1 Configuration Space register values.
  • This pattern repeats to cover all enabled PFs.
Figure 39. Configuration Output Interface Timing Diagram
Note: The P-Tile IP for PCIe provides a data link layer timer update output. Details on this signal are in the table below. When this signal asserts, you can sample the tl_cfg_ctl_o bus to see the new link speed, link width or max payload size and update the Replay/Ack-Nak timers accordingly.
Table 74.  Data Link Layer Timer Update Signal
Signal Name Direction Description Clock Domain EP/RP/BP
dl_timer_update_o O

Active high pulse that asserts whenever the current link speed, link width, or max payload size changes.

When any of these parameters changes, the IP's internal Replay/Ack-Nak timers default back to their internally calculated PCIe tables.

To override these default values, reprogram the Port Logic register when these events occur.

coreclkout_hip EP/RP/BP

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