P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.06.20 22.2 8.1.0
  • Added support for the Gen3 1x8 and Gen4 1x8 Endpoint modes.
  • Added the clarification that in 1x8 modes, the x8 port that is active is Port 0.
  • Added the constraint that when two-endpoint configurations are connected to independent hosts, P-tile expects the reference clock for both Port 0 and Port 1 to remain active during warm reset assertions following a global reset.
2022.03.28 22.1 8.0.0
  • Added Riviera* to the list of supported simulators in the Features section.
  • Updated the Overview section of Debug Toolkit to describe the dynamic switching between the User Avalon Memory-mapped Reconfiguration interface and the System Console-based Debug Toolkit when the latter is enabled.
  • Updated the block diagram in the Overview section of Debug Toolkit to show the addition of an arbitration multiplexer inside the P-tile Debug Toolkit module.
2021.12.13 21.4 7.0.0
  • Moved the signal surprise_down_err_o from the Power Management interface to the Hard IP Status interface.
  • Updated Completion buffer size values in the Completion Buffer Size section. Also updated the examples of Completion buffer entries consumed by Memory Read requests. Added a suggested flow diagram that the Application logic can follow to track the Completion buffer entries and schedule NP requests to the IP accordingly.
2021.10.07 21.3 6.0.0
  • Removed the sys_aux_pwr_det_i signal from the Hot Plug Interface. This signal is now in the Power Management Interface.
  • Updated the list of signals in the Power Management Interface section.
  • Updated the timing diagrams in the Configuration Registers Access section.
  • Added the instructions on how to use the Hard IP Reconfiguration Interface to enable and read ECRC and LCRC error event counters to the Additional Debug Tools section.
2021.07.06 21.2 5.0.0
  • Added 450 MHz as the maximum application clock frequency for Gen4 x4 and Gen4 x8 modes for Intel® Stratix® 10 DX devices.
  • Updated the lists of parameters for the TX path and RX path in the Debug Toolkit.
  • Added a note clarifying that RP and TLP Bypass modes are not supported by the Debug Toolkit in this release.
  • Added some signals to the Power Management Interface section: p#_sys_aux_pwr_det_i, apps_ready_entr_l23_i and app_xfer_pending_i.
  • Moved VirtIO parameters under the PCI Express and PCI Capabilities Parameters section.
2021.06.18 21.1 4.0.0
  • Updated the description of how the IP responds to transactions addressed to a function being reset by FLR in the Function Level Reset (FLR) section.
  • Updated the timing diagram in the Hard IP Reconfiguration Interface section.
2021.03.31 21.1 4.0.0
  • Updated the signal descriptions in the Power Management Interface section.
  • Added signals p<n>_cii_vf_num_o[10:0] and p<n>_cii_wr_vf_active_o to the Configuration Intercept Interface (EP Only) section.
  • Updated the description for signal flr_completed_vf_i in the Function-Level Reset (FLR) Interface section.
  • Updated the offsets and address ranges for Table 118 and Table 124 in the Configuration Space Registers Appendix chapter.
  • Added a note in the Top-Level Settings section stating that the independent reset feature will only be supported in a future release of Intel® Quartus® Prime.
2021.02.18 20.4 4.0.0 Replaced pin_perst_n with p<n>_pin_perst_n in the Table in section Signal Tap II Logic Analyzer.
2021.01.19 20.4 4.0.0

Updated the Hard IP Mode options in the Top-Level Settings section.

2020.12.18 20.4 4.0.0

Added Function-Level Reset (FLR) for PF and VF timing diagrams to the Function-Level Reset (FLR) section.

2020.12.14 20.4 4.0.0
  • Added parameters to enable the independent resets for the x8x8 bifurcated mode to the Parameters chapter.
  • Added a note specifying the default value of the Extended Tag field in the Device Capabilities register to the table in the SR-IOV Supported Features List section.
  • Updated the description of the p0_flr_completed_pf_i[7:0] signals in the Function-Level Reset (FLR) Interface (EP Only) section.
  • Updated the table Port Mode Options in TLP Bypass in the Top-Level Settings section to clarify the combinations in which TLP Bypass can be enabled or disabled when multiple ports are available.
  • Updated the directions of signals in the Avalon-ST TX Interface section to match the signal directions in the block symbol.
2020.10.05 20.3 3.1.0
  • Added descriptions for the Device Serial Number tab, the ACS tab to the Parameters chapter.
  • Updated the description of the p0_flr_rcvd_pf_o[7:0] signal bus in the Function-Level Reset (FLR) Interface section.
2020.07.10 20.2 3.0.0
  • Removed configurations that require the Adapter (Gen4 x8 512-bit and Gen4 x4 256-bit) from the Top-Level Settings section because they are not supported in the 20.2 release of Intel® Quartus® Prime.
  • Added description for the Link Inspector in the Debug Toolkit chapter.
  • Added support for the Modelsim simulator to the Features section.
2020.06.22 20.2 3.0.0
  • Added the lane reversal and polarity inversion support to the Features section.
  • Updated the bit ranges for the Next Capability Offset and Version fields in the Intel-Defined VSEC Capability Registers section.
  • Removed the Enable independent pin_perst parameter from the Avalon® Parameters section and the reset pin_perst_2_n from the Interface Reset Signals section. The independent pin_perst option is not supported in the 20.2 release of Intel® Quartus® Prime.
2020.04.30 20.1 2.0.0 Added clarification that VCS is the only simulator supported in the 20.1 release of Intel® Quartus® Prime. Also added a note stating that PIPE mode simulations are not supported in this release.
2020.04.29 20.1 2.0.0 Added notes to the Avalon® -ST RX Interface and Avalon® -ST TX Interface stating that the segmented (split) Avalon® -ST bus interface needs to be leveraged to achieve the expected Gen4 x16 performance.
2020.04.22 20.1 2.0.0
  • Updated the title of the document to Intel FPGA P-Tile Avalon® streaming IP for PCI Express* User Guide to meet new legal naming guidelines.
  • Added new parameters Enable Rx Buffer Limit Ports, P-tile Sim Mode and Enable independent pin_perst.
  • Added diagrams showing examples of buffer limits updates to the RX Flow Control Interface and TX Flow Control Interface sections.
  • Removed Notes stating that data parity is not supported because that feature is available in Intel® Quartus® Prime 20.1.
2020.01.16 19.4 1.1.0
  • Added information about the availability of the CvP Init and CvP Update features in Intel® Stratix® 10 DX and Intel® Agilex™ devices to the Features section.
  • Added the rx_st_tlp_abort_o[1:0] signals to the Avalon® -ST RX Interface section.
  • Removed the app_ready_entr_l23_i signal from the Power Management Interface section.
2019.12.16 19.4 1.1.0
  • Added parameters in Intel® Quartus® Prime to control PASID and LTR.
  • Added MSI extended data support.
2019.11.04 19.3 1.0.0
  • Added resource utilization numbers for the PIO design example in Intel® Stratix® 10 DX devices.
  • Added a step to select Intel® Stratix® 10 DX devices in the Generating the Design Example section.
2019.10.23 19.3 1.0.0
  • Added the description and usage instructions for the P-Tile Debug Toolkit.
  • Added an Appendix chapter on how to use the Avery BFM to run Gen4 x16 simulations.
2019.07.19 19.2 1.0.0 Added features such as SR-IOV support and VirtIO support.
2019.05.03 19.1.1   Initial release.

Did you find the information on this page useful?

Characters remaining:

Feedback Message