P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.12.2.2. Using the Debug Register Interface Access (Dword Access)

DEBUG_DBI_ADDR register is located at user Avalon® -MM offsets 0x104204 to 0x104207 (corresponding to byte 0 to byte 3).

Table 79.  DEBUG_DBI_ADDR Register
Names Bits Access Types Descriptions
d_done 31 RO 1: indicates debug DBI read/write access done
d_write 30 RW

1: write access

0: read access

d_warm_reset 29 RO

1: normal operation

0: warm reset is on-going

d_vf 28:18 RW Specify the virtual function number.
d_vf_select 17 RW To access the virtual function registers, set this bit to one.
d_pf 16:14 RW Specify the physical function number.
reserved 13:12 RW Reserved
d_addr 11:2 RW Specify the DW address for the P-Tile Hard IP DBI interface.
d_shadow_select 1 RW

Reserved. Clear this bit for access to standard PCIe configuration registers.

d_vsec_select 0 RW If set, this bit allows access to Intel VSEC registers.

DEBUG_DBI_DATA register is located at user Avalon® -MM offsets 0x104200 to 0x104203 (corresponding to byte 0 to byte 3).

Table 80.  DEBUG_DBI_DATA Register
Names Bits Access Types Descriptions
d_data 31:0 RW Read or write data for the P-Tile Hard IP register access.
To write all 32 bits in a Debug register at a time:
  1. Use the User Avalon-MM interface to access 0x104200 to 0x104203 to write the data first.
  2. Use the User Avalon-MM interface to access 0x104204 to 0x104206 to set the address and control bits.
  3. Use the User Avalon-MM interface to write to 0x104207 to enable the read/write bit (bit[30]).
  4. Use the User Avalon-MM interface to access 0x104207 bit[31] to poll if the write is complete.
Figure 46. DBI Register Write Timing Diagram
To read all 32 bits in a Debug register at a time:
  1. Use the user_avmm interface to access 0x104204 to 0x104206 to set the address and control bits.
  2. Use the user_avmm interface to write to 0x104207 to enable the read bit (bit[30]).
  3. Use the user_avmm interface to access 0x104207 bit[31] to poll if the read is complete.
  4. Use the user_avmm interface to access 0x104200 to 0x104203 to read the data.
Figure 47. DBI Register Read Timing Diagram

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