P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.9. Power Management Interface

The P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* IP core supports the required D0 and D3 Power Management states. It does not support the optional D1 and D2 Power Management states. Software programs the Device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management interface transmits the D-state to the Application Layer.

The correspondence between the device power states (D states) and link power states (L states) is as follows:

Table 70.  Relationship Between Device and Link Power States
Device Power State Link Power State
D0 L0
D1 (not supported) L1
D2 (not supported) L1
D3 L1, L2/L3 Ready

P-Tile does not support ASPM.

Endpoint D3 Entry
  1. The power management software must ensure that all outstanding non-posted requests have received their associated completions by polling that Transaction Pending bit in the Device Status register. Only then, it can put a function into the D3hot state by writing the appropriate value into the PowerState field of its Power Management Control and Status Register.
  2. The link is forced into the L1 state when all the enabled functions change to the D3hot state. In this state, the function can only initiate PME or PME_TO_ACK Messages and can only respond to configuration requests or the PME_Turn_Off Message.
  3. The power management software sends the PME_Turn_Off Message to the Endpoint to initiate power down. The delivery of the message TLP causes the link to transition to L0 and the Message will also be passed on to the Avalon® Streaming RX interface.
  4. The IP core automatically transmits a PME_TO_Ack Message to acknowledge the Turn Off request.
  5. When ready for the power removal D3cold state, the application logic in the Endpoint asserts p#_app_ready_entr_l23_i. The IP core will then send the PM_Enter_L23 DLLP and initiate the Link transition to L2/L3 Ready.
  6. The reference clock and power can finally be removed when the link has transitioned to the L23 Ready state.
Figure 37. Link Transition to L23 Ready

Endpoint D3 Exit

L1 exit:
  1. Initiated by Host : Power management software can write to the PowerState field of the function’s PMCSR register to change its PM state to D0. Alternatively, the host can initiate link retrain, link disable or hot reset for an L1 exit.
  2. Initiated by Device : For the Endpoint to exit the D3 state, the PME_en bit in the Power Management Control and Status (PMCSR) register needs to be set first. The Application Layer can then request a wake-up event by asserting apps_pm_xmt_pme_i, which causes the IP core to transmit a PM_PME Message. In addition, the IP core sets the PME_status bit in the PMCSR register to notify software that it has requested the wake-up. The PCIe Link states are indicated on the power management interface. The LTSSM state is indicated on the ltssm_state output.
Figure 38. Application Layer Requesting a Wake-up Event by Asserting apps_pm_xmt_pme_i

Endpoint L2 Exit

The L2 link state is not supported in P-tile. A power cycle for the FPGA is required to exit L2 state in this case.

Endpoint L3 Exit

A power cycle for the FPGA is required to exit L3 state.

Table 71.  Power Management Interface
Signal Name Direction Description Clock Domain EP/RP/BP
pm_state_o[2:0] O Indicates the current power state.
  • 3'b000 : L0 or IDLE
  • 3'b001 : L0s
  • 3'b010 : L1
  • 3'b011 : L2
  • 3'b100 : L3
  • Other values are invalid.
coreclkout_hip EP/RP/BP

x16/x8: pm_dstate_o[31:0]

x4: pm_dstate_o[3:0]

O

Power management D-state for each function.

Each PF uses four consecutive bits. For example, pm_dstate_o[3:0] correspond to PF0, pm_dstate_o[7:4] correspond to PF1, and so on.

The x4 ports (Ports 2 and 3) only require four bits to service a single PF. The D-states are encoded as follows:
  • 4'b0001 : D0
  • 4'b0010 : D1
  • 4'b0100 : D2
  • 4'b1000 : D3
  • Other values are invalid.
Async EP/RP/BP

x16/x8: apps_pm_xmt_pme_i[7:0]

x4: NA

I

The application logic asserts this signal for one cycle to wake up the Power Management Capability (PMC) state machine from a D1, D2, or D3 power state. Upon wake-up, the IP core sends a PM_PME message.

Each bit corresponds to a PF. For example, apps_pm_xmt_pme_i[0] is for PF0, apps_pm_xmt_pme_i[1] is for PF1, and so on.

coreclkout_hip EP/BP

x16/x8: app_ready_entr_l23_i

x4: NA

I The application logic asserts this signal to indicate that it is ready to enter the L2/L3 Ready state. The app_ready_entr_l23_i signal is provided for applications that must control the L2/L3 Ready entry (in case certain tasks must be performed before going into L2/L3 Ready). The core delays sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes active. This is a level-sensitive signal. coreclkout_hip EP/BP
apps_pm_xmt_turnoff_i I This signal is a request from the Application Layer to generate a PM_Turn_Off message. The Application Layer must assert this signal for one clock cycle. The IP core does not return an acknowledgement or grant signal. The Application Layer must not pulse the same signal again until the previous message has been transmitted. coreclkout_hip RP
app_init_rst_i I The Application Layer uses this signal to request a hot reset to downstream devices. The hot reset request will be sent when a single-cycle pulse is applied to this pin. coreclkout_hip RP
app_req_retry_en_i[x:0] where x = 7 for Port 0 and Port 1. For Port 2 and Port 3, this is a single-bit signal. I

When this signal is asserted, the PCIe Controller responds to Configuration TLPs with a CRS (Configuration Retry Status) if it has not already responded to a Configuration TLP with non-CRS status since the last reset. You can use this signal to hold off on enumeration. For Ports 2 and 3 which support Root Port mode only, this input is a single-bit signal.

Each bit corresponds to a PF. For example, app_req_retry_en_i[0] is for PF0, app_req_retry_en_i[1] is for PF1, and so on.

coreclkout_hip EP
p#_sys_aux_pwr_det_i I This is the Auxiliary Power Detected input (one signal for each port). It reports to the host software that auxiliary power (Vaux) is present. Refer to the Device Status Register in the PCI Express Capability Structure. Assertion of this signal will put the device into D3/L2 state instead of D3/L3 after L23_entry. Tie this signal to “0” as P-tile does not support the L2 state. coreclkout_hip EP/RP/BP
app_xfer_pending_i I This signal is only valid during L1 state. It is only used to make the device exit L1 and go back to L0. It is not able to prevent the device from entering L1. The PowerState field of the Power Management Control and Status Register takes higher precedence over this signal. It can trigger an L1 exit but the link will transition back to L1 again from L0 if the D3 state is not cleared. coreclkout_hip EP/RP/BP

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