P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces

The TLP prefix, header and data are sent and received on the TX and RX interfaces.

The ordering of bytes in the header and data portions of packets is different. The first byte of the header dword is located in the most significant byte of the dword. The first byte of the data dword is located in the least significant byte of the dword on the data bus.

Figure 15. Generic TLP Format
Figure 16. TLP Prefix, Header and Data on the RX and TX Interfaces of the P-Tile IP for PCIe

Did you find the information on this page useful?

Characters remaining:

Feedback Message