P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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7.1.1.3. Additional Debug Tools

Use the Hard IP reconfiguration interface and PHY reconfiguration interface on the P-Tile Avalon® -ST IP for PCI Express to access additional registers (for example, receiver detection, lane reversal etc.).

Figure 69. Register Access for Debug

Using the Hard IP Reconfiguration Interface

Refer to the section Hard IP Reconfiguration Interface for details on this interface and the associated address map.

The following table lists the address offsets and bit settings for the PHY status registers. Use the Hard IP Reconfiguration Interface to access these read-only registers.

Table 112.  Hard IP Reconfiguration Interface Register Map for PHY Status
Offset Bit Position Register
x16 (Port 0) x8 (Port 1)
0x0003E8 0x0003B0 [3:0] Lane select (0x0: Lane 0, 0x1: Lane 1, …, 0xF: Lane15)
0x0003EA 0x0003B2 [0] RX polarity
[1] RX detection
[2] RX Valid
[3] RX Electrical Idle
[4] TX Electrical Idle
0x0003EC 0x0003B4 [7] Framing error
0x0003ED 0x0003B5 [7] Lane reversal
Follow the steps below to access registers in Hard IP Reconfiguration Interface Register Map for PHY Status using the Hard IP reconfiguration interface:
  1. Enable the Hard IP reconfiguration interface (User Avalon® -MM interface) using the IP Parameter Editor.
  2. Set the lane number for which you want to read the status by performing a read-modify-write to the address hip_reconfig_addr_i[20:0] with write data of lane number on hip_reconfig_writedata_i[7:0] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_write_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E8
    • hip_reconfig_writedata_i[3:0] = <Lane number>, where Lane number = 4’h0 for lane 0, 4’h1 for lane 1, 4’h2 for lane 2, …
  3. Read the status of the register you want by performing a read operation from the address hip_reconfig_addr_i[20:0] using the Hard IP reconfiguration interface signals.
Example 1: To read the RX detection status of Lane0 using the registers
  1. Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x0003E8 to set the lane number to 0 using the Hard IP reconfiguration interface signals.
    • hip_reconfig_write_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E8
    • hip_reconfig_writedata_i[3:0] = 4'h0
  3. Read the status of the RX detection register by performing a read operation from the address 0x0003E9[1] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_read_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003EA
    • hip_reconfig_readdata_o[1] = 1'b1 (Far end receiver detected)

Using the Hard IP Reconfiguration Interface to Enable and Read ECRC and LCRC Error Counts

Table 113.  Hard IP Reconfiguration Interface Register Map for ECRC and LCRC Error Event Counters
Offset Bit Positions Register
x16 (Port 0) x8 (Port 1)
0x000119 0x000119 [0] Enable CRC Check
0x000340 0x000308 [1:0]

Event counter clear.

Set to 2'b01 to clear the specific event error counter defined in registers 0x00343and 0x00342.

Set to 2'b11 to clear all events' error counters.

[4:2]

Event counter enable.

Set to 3'b111.

0x000341 0x000309 [7:0]

Event counter lane select.

Set to 0x00.

0x000342 0x00030A [7:0]

Event number.

For LCRC error count, set to 0x01.

For ECRC error count, set to 0x02.

0x000343 0x00030B [7:0]

Group number.

For LCRC error count, set to 0x02.

For ECRC error count, set to 0x03.

0x000344 0x00030C [7:0] Error counter data bits [7:0].
0x000345 0x00030D [7:0] Error counter data bits [15:8].
0x000346 0x00030E [7:0] Error counter data bits [23:16].
0x000347 0x00030F [7:0] Error counter data bits [31:24].
Follow the steps below to access registers in the table above using the Hard IP Reconfiguration Interface:
  1. Enable the Hard IP Reconfiguration Interface (User Avalon-MM interface) using the IP Parameter Editor.
  2. Enable CRC check by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  3. Set the group number by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  4. Set the event number by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  5. Set the event counter lane select by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  6. Set event counter enable by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  7. Read the error count data by a read operation from the address p#_hip_reconfig_address[20:0].
Example: To read the LCRC error count of x16 Port0 using the registers:
  1. Enable the Hard IP Reconfiguration Interface (User Avalon-MM interface) using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x000119 to enable CRC check.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x000119
    • p0_hip_reconfig_writedata[7:0] = 8'h01
  3. Perform read-modify-write to address 0x000343 to set Group number.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x000343
    • p0_hip_reconfig_writedata[7:0] = 8'h02
  4. Perform read-modify-write to address 0x000342 to set Event number.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x000342
    • p0_hip_reconfig_writedata[7:0] = 8'h01
  5. Perform read-modify-write to address 0x000341 to set Event counter lane select.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x000341
    • p0_hip_reconfig_writedata[7:0] = 8'h00
  6. Perform read-modify-write to address 0x000340 to set enable event counter.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x000340
    • p0_hip_reconfig_writedata[7:0] = 8'h1C
  7. Read the error counter data by performing a read operation from registers 0x000344, 0x000345, 0x000346, and 0x000347.

Using the PHY Reconfiguration Interface

Refer to the section PHY Reconfiguration Interface for details on how to use this interface.

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