P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.12.1.1. User Avalon-MM Control Register (Offset 0x104068)

Table 78.  User Avalon-MM Control Register
Bits Register Description Default Value Access
[31:29] Reserved 0x0 RO
[28:18] Select the virtual function number. 0x0 RW
[17] To access the virtual function registers, this bit should be set to one. 0x0 RW
[16:2] Reserved 0x0 RO
[1]

Reserved. Clear this bit for access to standard PCIe* configuration registers.

0x0 RW
[0] If set, it allows access to Intel VSEC registers. 0x0 RW

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