P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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4.4. Avalon-ST Interface

The P-tile PCIe Hard IP provides an Avalon® -ST-like interface with separate header and data to improve the bandwidth utilization.

The Avalon® -ST interface has different data bus widths depending on the link width configuration of the PCIe IP.

Table 50.  Avalon-ST Interface Data and Header Bus Widths
PCIe Link Width Data Width (bits) Header Width (bits) TLP Prefix Width (bits)
x16 512 (2 x 256) 256 (2 x 128) 64 (2 x 32)
x8 256 128 32
x4 128 128 32
Note:
  • For the x16 configuration, two segments of 256-bit data and two segments of 128-bit header are available.
  • x4 configuration is only present in Root Port mode.

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