4.4.6. Avalon® -ST TX Interface tx_st_ready Behavior
The following timing diagram illustrates the behavior of tx_st_ready_o, which is deasserted to pause the data transmission to the Transaction Layer of the P-Tile IP for PCIe, and then reasserted. The timing diagram shows a readyLatency of three cycles. The application deasserts tx_st_valid_i three cycles after tx_st_ready_o is deasserted.
The application must not deassert tx_st_valid_i between tx_st_sop_i and tx_st_eop_i on a ready cycle unless there is backpressure with the deassertion of tx_st_ready_o. A ready cycle is a cycle during which the sink can accept a transfer.
Did you find the information on this page useful?