P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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3.3.1. Overview

When the TLP Bypass feature is enabled, the P-Tile Avalon® -ST IP does not process received TLPs internally but outputs them to the user application. This allows the application to implement a custom Transaction Layer.

Note that in TLP Bypass mode, the PCIe Hard IP does not generate/check the ECRC and will not remove it if the received TLP has the ECRC.

The P-tile Avalon® -ST IP in TLP Bypass mode still includes some of the PCIe configuration space registers related to link operation (refer to the Configuration Space Registers chapter for the list of registers).

P-Tile interfaces with the application logic via the Avalon® -ST interface (for all TLP traffic), the User Avalon® -MM interface (for Lite TL’s configuration registers access) and other miscellaneous signals.
Figure 12. P-Tile Avalon® -ST IP in TLP Bypass Mode

In TLP bypass mode, P-Tile supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code.

However, in TLP bypass mode, CvP init and update are not supported.

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