P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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5.2.1. Avalon® Parameters

Table 85.   Avalon® Parameters
Parameter Value Default Value Description
Enable Power Management Interface and Hard IP Status Interface True/False False

When enabled, the Power Management Interface and Hard IP Status Interface are exported. For more details, refer to section Power Management Interface.

In addition, options are provided to add the following signals for power management depending on the selected port mode of the IP: p#_apps_ready_entr_l23_i, p#_app_xfer_pending_i, p#_apps_pm_xmt_turnoff_i.

Enable Legacy Interrupt True/False False

Enable the support for legacy interrupts. For more details, refer to section Legacy Interrupts.

Enable Completion Timeout Interface True/False False Enable the Completion Timeout Interface. For more details, refer to section Completion Timeout Interface.
Enable Configuration Intercept Interface True/False False Enable the Configuration Intercept Interface. For more details, refer to section Configuration Intercept Interface (EP Only).
Note: This parameter is only available in EP mode.
Enable PRS Event True/False False Enable the Page Request Service (PRS) Event Interface. For more details, refer to section Page Request Service (PRS) Interface (EP Only).
Note: This parameter is only available in EP mode.
Enable Error Interface True/False False

Enable the Error Interface. For more details, refer to section Error Interface.

Enable Hot Plug True/False False

Enable the Hot Plug Interface.

Note: This interface is only available in RP mode.
Enable 10-bit Tag Support Interface True/False False When this parameter is enabled, the 10-bit tag request enable signal is enabled as an output port p0_10bits_tag_req_en_o[7:0] (one bit per PF). Refer to Tag Allocation for more details.
Enable Hard IP Reconfiguration Interface True/False False Enable the Hard IP Reconfiguration Avalon Memory-mapped (Avalon-MM) slave interface.
Note: This interface is always enabled in the Root Port or TLP Bypass mode. However, in Endpoint mode, you can choose to enable it or not using this parameter.
Enable Byte Parity Ports on Avalon® -ST Interface True/False False When this parameter is enabled, the byte parity ports appear on the block symbol. These byte parity ports include: rx_st_data_par_o, rx_st_hdr_par_o, rx_st_tlp_prfx_par_o, tx_st_data_par_o, tx_st_hdr_par_o, and tx_st_tlp_prfx_par_o ports.

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