P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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Document Table of Contents

4.1. Overview

You can determine which core each interface in this section belongs to by looking at the prefixes in the signal names:
  • p0 : x16 core
  • p1 : x8 core
  • p2 : x4_0 core
  • p3 : x4_1 core

P-Tile Avalon® -ST IP for PCI Express* Top-Level Signals shows the top-level signals of this IP. Note that the signal names in the figure get the appropriate prefix pn (where n = 0, 1, 2 or 3) depending on which of the three supported configurations (1x16, 2x8, or 4x4) the P-Tile Avalon® -ST IP for PCI Express* is in.

As an example, the rx_st_data_o bus can take on the following names:
  • In the 1x16 configuration, only the x16 core is active. In this case, this bus appears as p0_rx_st_data_o[511:0].
  • In the 1x8 configuration, only the x16 core is active. In this case, this bus appears as p0_rx_st_data_o[255:0].
  • In the 2x8 configuration, both the x16 core and x8 core are active. In this case, this bus is split into p0_rx_st_data_o[255:0] and p1_rx_st_data_o[255:0].
  • In the 4x4 configuration, all four cores are active. In this case, this bus is split into p0_rx_st_data_o[127:0], p1_rx_st_data_o[127:0], p2_rx_st_data_o[127:0] and p3_rx_st_data_o[127:0].

The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like the PHY reconfiguration interface, clocks and resets. For example, there is only one xcvr_reconfig_clk that is shared by all the cores.

You can enable the PHY reconfiguration interface from the Top Level Settings in the GUI.

Each of the cores has its own Avalon® -ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes:

Table 44.  IP to FPGA Fabric Interfaces Summary
Mode Avalon-ST Interface Count Data Width (each Interface) Header Width (each Interface) TLP Prefix Width (each Interface) Application Clock Frequency
Gen4 x16 EP/RP mode 1 512-bit 256-bit 64-bit

175 MHz / 200 MHz / 225 MHz / 350 MHz / 400 MHz / 450 MHz ( Intel® Stratix® 10 DX)

175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz ( Intel® Agilex™ )

3
Gen3 x16 EP/RP mode 1 512-bit 256-bit 64-bit 250 MHz
Gen3 x16 EP/RP mode 1 256-bit 128-bit 32-bit 250 MHz 4
Gen4 1x8 EP mode 1 256-bit 128-bit 32-bit 350 MHz / 400 MHz / 450 MHz / 500 MHz
Gen4 x8 x8 EP mode 2 256-bit 128-bit 32-bit

175 MHz / 200 MHz / 225 MHz / 350 MHz / 400 MHz / 450 MHz ( Intel® Stratix® 10 DX)

175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz ( Intel® Agilex™ )

3
Gen4 x8 x8 EP mode 2 512-bit 256-bit 64-bit

175 MHz / 200 MHz / 225 MHz ( Intel® Stratix® 10 DX)

175 MHz / 200 MHz / 225 MHz / 250 MHz ( Intel® Agilex™ )

3
Gen3 1x8 EP mode 1 256-bit 128-bit 32-bit 250 MHz
Gen3 x8 x8 EP mode 2 256-bit 128-bit 32-bit 250 MHz
Gen4 x4 x4 x4 x4 RP mode 4 128-bit 128-bit 32-bit

350 MHz / 400 MHz / 450 MHz ( Intel® Stratix® 10 DX)

350 MHz / 400 MHz / 450 MHz / 500 MHz ( Intel® Agilex™ )

3
Gen3 x4 x4 x4 x4 RP mode 4 128-bit 128-bit 32-bit 250 MHz
Figure 14. P-Tile Avalon® -ST IP for PCI Express* Top-Level Signals
Note: The table below shows the variables that are used to define the bus indices for top-level signal busses shown in the top-level block diagram above. The values of these variables change depending on which configuration is active (1x16, 1x8, 2x8 or 4x4). For example, for the 4x4 configuration, using w=1 and n=1 gives Avalon® -ST RX bus widths of p0_rx_st_data_o[127:0], p0_rx_st_hdr_o[127:0] and p0_rx_st_tlp_prfx_o[31:0].
Table 45.  Variables Used in the Bus Indices
Variable 1x16 Configuration 1x8 and 2x8 Configurations 4x4 Configuration
w 4 2 1
n 2 1 1
p 6 3 2
b 16 16 4
3 Select the highest clock frequency to achieve maximum PCIe Gen4 bandwidth.
4 In this configuration, interface efficiency is traded off for lower interface width.

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