P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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Document Table of Contents

A.1. Configuration Space Registers

In addition to accessing the Endpoint's configuration space registers by sending Configuration Read/Write TLPs via the Avalon® -ST interface, the application logic can also gain read access to these registers via the Configuration Output Interface (tl_cfg*). Furthermore, the Hard IP Reconfiguration Interface (a User Avalon® -MM interface) also provides read/write access to these registers.

For signal timings on the User Avalon® -MM interface, refer to the Avalon® Interface Specifications document.

The table PCIe Configuration Space Registers describes the registers for each PF. To calculate the address for a particular register in a particular PF, add the offset for that PF from the table Configuration Space Offsets to the byte address for that register as given in the table PCIe Configuration Space Registers.

Table 122.  Configuration Space Offsets
Registers User Avalon® -MM Offsets
Physical function 0 0x0000
Physical function 1 0x1000
Physical function 2 0x2000
Physical function 3 0x3000
Physical function 4 0x4000
Physical function 5 0x5000
Physical function 6 0x6000
Physical function 7 0x7000
User Avalon-MM Control Register 0x104068
Debug (DBI) Register 0x104200, 0x104204
Note: In 1x8 EP mode, only the x16 (Port 0) core is active.
Table 123.  PCIe Configuration Space Registers for x16/x8/x4 Controllers
Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

x16 (Port 0) = 0x000 : 0x03C

x8 (Port 1) = 0x000 : 0x03C

x4 (Ports 2,3) = 0x000 : 0x03C

PCI Header Type 0/1 Configuration Registers Type 0/1 Configuration Space Header

x16 (Port 0) = 0x040 : 0x044

x8 (Port 1) = 0x040 : 0x044

x4 (Ports 2,3) = 0x040 : 0x044

Power Management PCI Power Management Capability Structure

x16 (Port 0) = 0x050 : 0x064

x8 (Port 1) = 0x050 : 0x064

x4 (Ports 2,3) = 0x050 : 0x05c

MSI Capability

MSI Capability Structure, see also PCI Local Bus Specification

x16 (Port 0) = 0x070 : 0x0A8

x8 (Port 1) = 0x070 : 0x0A8

x4 (Ports 2,3) = 0x070 : 0x0A8

PCI Express Capability PCI Express Capability Structure

x16 (Port 0) = 0x0B0 : 0x0B9

x8 (Port 1) = 0x0B0 : 0x0B9

x4 (Ports 2,3) = 0x0B0 : 0x0B9

MSI-X Capability MSI-X Capability Structure, see also PCI Local Bus Specification

x16 (Port 0) = 0x0BC : 0x0FC

x8 (Port 1) = 0x0BC : 0x0FC

x4 (Ports 2,3) = 0x0BC : 0x0FC

Reserved N/A

x16 (Port 0) = 0x100 : 0x144

x8 (Port 1) = 0x100 : 0x144

x4 (Ports 2,3) = 0x100 : 0x144

Advanced Error Reporting (AER) Advanced Error Reporting Capability Structure

x16 (Port 0) = 0x148 : 0x164

x8 (Port 1) = 0x148 : 0x164

x4 (Ports 2,3) = 0x148 : 0x164

Virtual Channel Capability Virtual Channel Capability Structure

x16 (Port 0) = 0x178 : 0x17C

x8 (Port 1) = 0x178 : 0x17C

x4 (Ports 2,3) = N/A

Alternative Routing-ID Implementation (ARI) ARI Capability Structure

x16 (Port 0) = 0x188 : 0x1B4

x8 (Port 1) = 0x188 : 0x1A4

x4 (Ports 2,3) = 0x188 : 0x1A4

Secondary PCI Express Extended Capability Header

PCI Express Extended Capability

x16 (Port 0) = 0x1B8 : 0x1E4

x8 (Port 1) = 0x1A8 : 0x1CC

x4 (Ports 2,3) = 0x1A8 : 0x1C8

Physical Layer 16.0 GT/s Extended Capability Physical Layer 16.0 GT/s Extended Capability Structure

x16 (Port 0) = 0x1E8 : 0x22C

x8 (Port 1) = 0x1D0 : 0x1F4

x4 (Ports 2,3) = 0x1CC : 0x1E0

Margining Extended Capability Margining Extended Capability Structure

x16 (Port 0) = 0x230 : 0x26C

x8 (Port 1) = 0x1F8 : 0x234

x4 (Ports 2,3) = N/A

SR-IOV Capability SR-IOV Capability Structure

x16 (Port 0) = 0x270 : 0x2F8

x8 (Port 1) = 0x238 : 0x2C0

x4 (Ports 2,3) = 0x1E4 : 0x26C

TLP Processing Hints (TPH) Capability TLP Processing Hints (TPH) Capability Structure

x16 (Port 0) = 0x2FC : 0x300

x8 (Port 1) = 0x2C4 : 0x2C8

x4 (Ports 2,3) = N/A

Address Translation Services (ATS) Capability Address Translation Services Extended Capability (ATS) in Single Root I/O Virtualization and Sharing Specification

x16 (Port 0) = 0x30C : 0x314

x8 (Port 1) = 0x2D4 : 0x2DC

x4 (Ports 2,3) = 0x280 : 0x288

Access Control Services (ACS) Capability Access Control Services (ACS) Capability

x16 (Port 0) = 0x318 : 0x324

x8 (Port 1) = 0x2E0 : 0x2EC

x4 (Ports 2,3) = N/A

Page Request Services (PRS) Capability Page Request Services (PRS) Capability

x16 (Port 0) = 0x328 : 0x32C

x8 (Port 1) = 0x2F0 : 0x2F4

x4 (Ports 2,3) = N/A

Latency Tolerance Reporting (LTR) Capability Latency Tolerance Reporting (LTR) Capability

x16 (Port 0) = 0x330 : 0x334

x8 (Port 1) = 0x2F8 : 0x2FC

x4 (Ports 2,3) = N/A

Process Address Space (PASID) Capability Process Address Space (PASID) Capability Structure

x16 (Port 0) = 0x338 : 0x434

x8 (Port 1) = 0x300 : 0x3FC

x4 (Ports 2,3) = 0x2AC : 0x3A8

RAS D.E.S. Capability (VSEC)  

x16 (Port 0) = 0x470 : 0x478

x8 (Port 1) = 0x438 : 0x440

x4 (Ports 2,3) = 0x3E4 : 0x3EC

Data Link Feature Extended Capability  

x16 (Port 0) = 0xD00 : 0xD58

x8 (Port 1) = 0xD00 : 0xD58

x4 (Ports 2,3) = 0xD00 : 0xD58

Intel-defined VSEC  

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