2.2.3. Transaction Layer Overview
The following figure shows the major blocks in the P-Tile Avalon® -ST IP for PCI Express Transaction Layer:
The RAS (Reliability, Availability, and Serviceability) block includes a set of features to maintain the integrity of the link.
For example: Transaction Layer inserts an optional ECRC in the transmit logic and checks it in the receive logic to provide End-to-End data protection.
When the application logic sets the TLP Digest (TD) bit in the Header of the TLP, the P-Tile Avalon® -ST IP for PCIe will append the ECRC automatically.
Note that in TLP Bypass mode, the PCIe Hard IP does not generate/check the ECRC and will not remove it if the received TLP has the ECRC.
The TX block sends out the TLPs that it receives as-is. It also sends the information about non-posted TLPs to the CPL Timeout Block for CPL timeout detection.
- Filtering block: This module checks if the TLP is good or bad and generates the associated error message and completion. It also tracks received completions and updates the completion timeout (CPL timeout) block.
- RX Buffer Queue: The P-Tile IP for PCIe has separate queues for posted/non-posted transactions and completions. This avoids head-of-queue blocking on the received TLPs and provides flexibility to extract TLPs according to the PCIe ordering rules.
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