Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents

2.3.5. Passive Serial Configuration Timing

Figure 32. PS Configuration Timing Waveform Timing waveform for a passive serial (PS) configuration when using a MAX® II device, MAX® V device, or microprocessor as an external host.
Table 138.  PS Timing Parameters for Arria V GZ Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low 600 ns
tCF2ST0 nCONFIG low to nSTATUS low 600 ns
tCFG nCONFIG low pulse width 2 μs
tSTATUS nSTATUS low pulse width 268 1,506 223 μs
tCF2ST1 nCONFIG high to nSTATUS high 1,506 224 μs
tCF2CK 225 nCONFIG high to first rising edge on DCLK 1,506 μs
tST2CK 225 nSTATUS high to first rising edge of DCLK 2 μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 ns
tDH DATA[] hold time after rising edge on DCLK 0 ns
tCH DCLK high time 0.45 × 1/fMAX s
tCL DCLK low time 0.45 × 1/fMAX s
tCLK DCLK period 1/fMAX s
fMAX DCLK frequency 125 MHz
tCD2UM CONF_DONE high to user mode 226 175 437 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (8576 × CLKUSR period) 227
223 This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
224 This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
225 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
226 The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
227 To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the Initialization section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.