Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents

2.3.4. Active Serial Configuration Timing

Figure 31. AS Configuration TimingTiming waveform for the active serial (AS) x1 mode and AS x4 mode configuration timing.
Table 136.  AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices

The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.

tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in the "PS Timing Parameters for Arria V GZ Devices" table.

Symbol Parameter Condition Minimum Maximum Unit
tCO 220 DCLK falling edge to AS_DATA0/ASDO output 4 ns
tSU 221 Data setup time before falling edge on DCLK 1.5 ns
tDH 221 Data hold time after falling edge on DCLK –3 speed grade 3.7 ns
–4 speed grade 3.9 ns
tCD2UM CONF_DONE high to user mode 222 175 437 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (8576 × CLKUSR period)
Table 137.  DCLK Frequency Specification in the AS Configuration Scheme

This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.

The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.

Minimum Typical Maximum Unit
5.3 7.9 12.5 MHz
10.6 15.7 25.0 MHz
21.3 31.4 50.0 MHz
42.6 62.9 100.0 MHz
220 Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, and termination resistors) through IBIS or HSPICE simulation.
221 To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline.
222 To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the “Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.