Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents DQS Logic Block Specifications

Table 44.  DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria® V DevicesThis error specification is the absolute maximum and minimum error.
Number of DQS Delay Buffer –I3, –C4 –I5, –C5 –C6 Unit
2 40 80 80 ps