Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents DQS Logic Block Specifications

Table 126.  DQS Phase Offset Delay Per Setting for Arria V GZ Devices

The typical value equals the average of the minimum and maximum values.

The delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when using a –3 speed grade and applying a 10-phase offset setting to a 90° phase shift at 400 MHz, the expected average cumulative delay is [625 ps + (10 × 11 ps) ± 20 ps] = 735 ps ± 20 ps.

Speed Grade Min Max Unit
C3, I3L 8 15 ps
C4, I4 8 16 ps
Table 127.  DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V GZ DevicesThis error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –3 speed grade is ±84 ps or ±42 ps.
Number of DQS Delay Buffers C3, I3L C4, I4 Unit
1 30 32 ps
2 60 64 ps
3 90 96 ps
4 120 128 ps

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