Arria® V Device Datasheet

Download PDF
ID 683022
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
1. Arria® V GX, GT, SX, and ST Device Datasheet 2. Arria V GZ Device Datasheet
1. Arria® V GX, GT, SX, and ST Device Datasheet x
1.1. Electrical Characteristics 1.2. Switching Characteristics 1.3. Configuration Specifications 1.4. I/O Timing 1.5. Glossary 1.6. Arria® V GX, GT, SX, and ST Device Datasheet Revision History
1.1. Electrical Characteristics x
1.1.1. Operating Conditions
1.1.1. Operating Conditions x
1.1.1.1. Absolute Maximum Ratings 1.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 1.1.1.3. Recommended Operating Conditions 1.1.1.4. DC Characteristics 1.1.1.5. I/O Standard Specifications
1.1.1.3. Recommended Operating Conditions x
1.1.1.3.1. Recommended Operating Conditions 1.1.1.3.2. Transceiver Power Supply Operating Conditions 1.1.1.3.3. HPS Power Supply Operating Conditions
1.1.1.4. DC Characteristics x
1.1.1.4.1. Supply Current and Power Consumption 1.1.1.4.2. I/O Pin Leakage Current 1.1.1.4.3. Bus Hold Specifications 1.1.1.4.4. OCT Calibration Accuracy Specifications 1.1.1.4.5. OCT Without Calibration Resistance Tolerance Specifications 1.1.1.4.6. OCT Variation after Power-Up Calibration 1.1.1.4.7. Pin Capacitance 1.1.1.4.8. Hot Socketing 1.1.1.4.9. Internal Weak Pull-Up Resistor
1.1.1.5. I/O Standard Specifications x
1.1.1.5.1. Single-Ended I/O Standards 1.1.1.5.2. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications 1.1.1.5.3. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 1.1.1.5.4. Differential SSTL I/O Standards 1.1.1.5.5. Differential HSTL and HSUL I/O Standards 1.1.1.5.6. Differential I/O Standard Specifications
1.2. Switching Characteristics x
1.2.1. Transceiver Performance Specifications 1.2.2. Core Performance Specifications 1.2.3. Periphery Performance 1.2.4. HPS Specifications
1.2.1. Transceiver Performance Specifications x
1.2.1.1. Transceiver Specifications for Arria V GX and SX Devices 1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices 1.2.1.3. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.5. Typical TX VOD Setting for Arria® V Transceiver Channels with termination of 100 Ω 1.2.1.6. Transmitter Pre-Emphasis Levels 1.2.1.7. Transceiver Compliance Specification
1.2.2. Core Performance Specifications x
1.2.2.1. Clock Tree Specifications 1.2.2.2. PLL Specifications 1.2.2.3. DSP Block Performance Specifications 1.2.2.4. Memory Block Performance Specifications 1.2.2.5. Internal Temperature Sensing Diode Specifications
1.2.3. Periphery Performance x
1.2.3.1. High-Speed I/O Specifications 1.2.3.2. DPA Lock Time Specifications 1.2.3.3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications 1.2.3.4. DLL Frequency Range Specifications 1.2.3.5. DQS Logic Block Specifications 1.2.3.6. Memory Output Clock Jitter Specifications 1.2.3.7. OCT Calibration Block Specifications 1.2.3.8. Duty Cycle Distortion (DCD) Specifications
1.2.4. HPS Specifications x
1.2.4.1. HPS Clock Performance 1.2.4.2. HPS PLL Specifications 1.2.4.3. Quad SPI Flash Timing Characteristics 1.2.4.4. SPI Timing Characteristics 1.2.4.5. SD/MMC Timing Characteristics 1.2.4.6. USB Timing Characteristics 1.2.4.7. Ethernet Media Access Controller (EMAC) Timing Characteristics 1.2.4.8. I2C Timing Characteristics 1.2.4.9. NAND Timing Characteristics 1.2.4.10. Arm* Trace Timing Characteristics 1.2.4.11. UART Interface 1.2.4.12. GPIO Interface 1.2.4.13. HPS JTAG Timing Specifications
1.2.4.2. HPS PLL Specifications x
1.2.4.2.1. HPS PLL VCO Frequency Range 1.2.4.2.2. HPS PLL Input Clock Range 1.2.4.2.3. HPS PLL Input Jitter
1.3. Configuration Specifications x
1.3.1. POR Specifications 1.3.2. FPGA JTAG Configuration Timing 1.3.3. FPP Configuration Timing 1.3.4. Active Serial (AS) Configuration Timing 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme 1.3.6. Passive Serial (PS) Configuration Timing 1.3.7. Initialization 1.3.8. Configuration Files 1.3.9. Minimum Configuration Time Estimation 1.3.10. Remote System Upgrades 1.3.11. User Watchdog Internal Oscillator Frequency Specifications
1.3.3. FPP Configuration Timing x
1.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 1.3.3.2. FPP Configuration Timing when DCLK-to-DATA[] = 1 1.3.3.3. FPP Configuration Timing when DCLK-to-DATA[] >1
1.4. I/O Timing x
1.4.1. Programmable IOE Delay 1.4.2. Programmable Output Buffer Delay
2. Arria V GZ Device Datasheet x
2.1. Electrical Characteristics 2.2. Switching Characteristics 2.3. Configuration Specification 2.4. I/O Timing 2.5. Glossary 2.6. Arria® V GZ Device Datasheet Revision History
2.1. Electrical Characteristics x
2.1.1. Operating Conditions
2.1.1. Operating Conditions x
2.1.1.1. Absolute Maximum Ratings 2.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 2.1.1.3. Recommended Operating Conditions 2.1.1.4. DC Characteristics 2.1.1.5. I/O Standard Specifications
2.1.1.3. Recommended Operating Conditions x
2.1.1.3.1. Recommended Transceiver Power Supply Operating Conditions 2.1.1.3.2. Transceiver Power Supply Requirements
2.1.1.4. DC Characteristics x
2.1.1.4.1. Supply Current 2.1.1.4.2. Power Consumption 2.1.1.4.3. I/O Pin Leakage Current 2.1.1.4.4. Bus Hold Specifications 2.1.1.4.5. On-Chip Termination (OCT) Specifications 2.1.1.4.6. Pin Capacitance 2.1.1.4.7. Hot Socketing 2.1.1.4.8. Internal Weak Pull-Up Resistor
2.2. Switching Characteristics x
2.2.1. Transceiver Performance Specifications 2.2.2. Core Performance Specifications 2.2.3. Periphery Performance
2.2.1. Transceiver Performance Specifications x
2.2.1.1. Reference Clock 2.2.1.2. Transceiver Clocks 2.2.1.3. Receiver 2.2.1.4. Transmitter 2.2.1.5. CMU PLL 2.2.1.6. ATX PLL 2.2.1.7. Fractional PLL 2.2.1.8. Clock Network Data Rate 2.2.1.9. Standard PCS Data Rate 2.2.1.10. 10G PCS Data Rate 2.2.1.11. Typical VOD Settings
2.2.2. Core Performance Specifications x
2.2.2.1. Clock Tree Specifications 2.2.2.2. PLL Specifications 2.2.2.3. DSP Block Specifications 2.2.2.4. Memory Block Specifications 2.2.2.5. Temperature Sensing Diode Specifications
2.2.3. Periphery Performance x
2.2.3.1. High-Speed I/O Specification 2.2.3.2. DLL Range Specifications 2.2.3.3. DQS Logic Block Specifications 2.2.3.4. Memory Output Clock Jitter Specifications 2.2.3.5. OCT Calibration Block Specifications 2.2.3.6. Duty Cycle Distortion (DCD) Specifications
2.2.3.1. High-Speed I/O Specification x
2.2.3.1.1. High-Speed Clock Specifications 2.2.3.1.2. Transmitter High-Speed I/O Specifications 2.2.3.1.3. Receiver High-Speed I/O Specifications 2.2.3.1.4. DPA Mode High-Speed I/O Specifications 2.2.3.1.5. Soft CDR Mode High-Speed I/O Specifications 2.2.3.1.6. Non DPA Mode High-Speed I/O Specifications
2.3. Configuration Specification x
2.3.1. POR Specifications 2.3.2. JTAG Configuration Specifications 2.3.3. Fast Passive Parallel (FPP) Configuration Timing 2.3.4. Active Serial Configuration Timing 2.3.5. Passive Serial Configuration Timing 2.3.6. Initialization 2.3.7. Configuration Files 2.3.8. Remote System Upgrades Circuitry Timing Specification 2.3.9. User Watchdog Internal Oscillator Frequency Specification
2.3.3. Fast Passive Parallel (FPP) Configuration Timing x
2.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 2.3.3.2. FPP Configuration Timing when DCLK to DATA[] = 1 2.3.3.3. FPP Configuration Timing when DCLK to DATA[] > 1
2.4. I/O Timing x
2.4.1. Programmable IOE Delay 2.4.2. Programmable Output Buffer Delay
1. Arria® V GX, GT, SX, and ST Device Datasheet
2. Arria V GZ Device Datasheet

2.6. Arria® V GZ Device Datasheet Revision History

Document Version Changes
2019.04.26 Added a note for Conversion Time in the Internal Temperature Sensing Diode Specification for Arria V GZ Devices table.
2019.01.25
  • Added Arria® V GZ Devices Overshoot Duration diagram.
  • Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Arria® V GZ Devices table.
  • Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Arria® V GZ Devices table.
    • Updated tDH specifications. These specifications are applicable to the commercial and industrial grade devices.
    • Added note to tCO, tSU, and tDH.
  • Changed instances of Quartus II to Intel Quartus Prime.
  • Removed PowerPlay text from tool name.
  • Renamed IP cores as per Intel rebranding.
Date Version Changes
February 2017 2017.02.10
  • Changed the minimum value for tCD2UMC in the “FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1” table.
  • Changed the minimum value for tCD2UMC in the "FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1" table.
  • Changed the minimum value for tCD2UMC in the "AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices" table.
  • Changed the minimum value for tCD2UMC in the "PS Timing Parameters for Arria V GZ Devices" table.
  • Changed the minimum number of clock cycles value in the "Initialization Clock Source Option and the Maximum Frequency for Arria V GZ Devices" table.
June 2016 2016.06.20
  • Changed column heading from "Value" to "Maximum" in the "Pin Capacitance for Arria V GZ Devices" table.
  • Changed the minimum supported data rate range values from "1000" to "2000" in the "ATX PLL Specifications for Arria V GZ Devices" table.
  • Added the supported data rates for the following output standards using true LVDS output buffer types in the "High-Speed Clock Specifications for Arria® V GZ Devices" table:
    • True RSDS output standard: data rates of up to 230 Mbps
    • True mini-LVDS output standard: data rates of up to 340 Mbps
December 2015 2015.12.16
  • Removed the CDR ppm tolerance specification from the "Receiver Specifications for Arria V GZ Devices" table.
  • Removed transmitter rise and fall time specifications from the "Transmitter Specifications for Arria V GZ Devices" table.
  • Changed the .rbf sizes in the "Uncompressed .rbf Sizes for Arria V GZ Devices" table.
  • Added a footnote to the "Transmitter High-Speed I/O Specifications for Arria V GZ Devices" table.
June 2015 2015.06.16
  • Changed the conditions for the reference clock rise and fall time and added a note to the condition in the "Reference Clock Specifications for Arria V GZ Devices" table.
  • Added a note to the "Minimum differential eye opening at receiver serial input pins" specification in the "Receiver Specifications for Arria V GZ Devices" table.
January 2015 2015.01.30
  • Added 240-Ω to the "OCT Calibration Accuracy Specifications for Arria V GZ Devices" table.
  • Changed the CDR PPM tolerance spec in the "Receiver Specifications for Arria V GZ Devices" table.
  • Added additional max data rate for fPLL in the "Fractional PLL Specifications for Arria V GZ Devices" table.
July 2014 3.8
  • Updated Table 21.
  • Updated Table 22 VOCM (DC Coupled) condition.
  • Updated the DCLK note to Figure 6, Figure 7, and Figure 9.
  • Added note to Table 5 and Table 6.
  • Added the DCLK specification to Table 50.
  • Added note to Table 51.
  • Updated the list of parameters in Table 53.
February 2014 3.7 Updated Table 28.
December 2013 3.6
  • Updated Table 2, Table 13, Table 18, Table 19, Table 22, Table 30, Table 33, Table 37, Table 38, Table 45, Table 46, Table 47, Table 56, Table 49.
  • Updated “PLL Specifications”.
August 2013 3.5 Updated Table 28.
August 2013 3.4
  • Removed Preliminary tags for Table 2, Table 4, Table 5, Table 14, Table 27, Table 28, Table 29, Table 31, Table 32, Table 43, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, and Table 54.
  • Updated Table 2 and Table 28.
June 2013 3.3 Updated Table 23, Table 28, Table 51, and Table 55.
May 2013 3.2
  • Added Table 23.
  • Updated Table 5, Table 22, Table 26, and Table 57.
  • Updated Figure 6, Figure 7, Figure 8, and Figure 9.
March 2013 3.1
  • Updated Table 2, Table 6, Table 7, Table 8, Table 19, Table 22, Table 26, Table 29, Table 52.
  • Updated “Maximum Allowed Overshoot and Undershoot Voltage”.
December 2012 3.0 Initial release.
Level Two Title