Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents CMU PLL

Table 104.  CMU PLL Specifications for Arria V GZ DevicesSpeed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit
Min Typ Max Min Typ Max
Supported data range 600 12500 600 10312.5 Mbps
tpll_powerdown 156 1 1 µs
tpll_lock 157   10 10 µs
156 tpll_powerdown is the PLL powerdown minimum pulse width.
157 tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.

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