Arria® V Device Datasheet

ID 683022
Date 5/23/2023
Document Table of Contents Transmitter High-Speed I/O Specifications

Table 118.  Transmitter High-Speed I/O Specifications for Arria V GZ Devices

When J = 3 to 10, use the serializer/deserializer (SERDES) block.

When J = 1 or 2, bypass the SERDES block.

Symbol Conditions C3, I3L C4, I4 Unit
Min Typ Max Min Typ Max
True Differential I/O Standards - fHSDR (data rate) SERDES factor J = 3 to 10 186, 187 188 1250 188 1050 Mbps
SERDES factor J ≥ 4


189, 190, 191, 192
188 1600 188 1250 Mbps
SERDES factor J = 2, 
uses DDR Registers 188 193 188 193 Mbps
SERDES factor J = 1, 
uses SDR Register 188 193 188 193 Mbps
Emulated Differential I/O Standards with Three External Output Resistor Networks - fHSDR (data rate) 194 SERDES factor J = 4 to 10 195 188 840 188 840 Mbps
tx Jitter - True Differential I/O Standards Total Jitter for Data Rate 600 Mbps - 1.25 Gbps 160 160 ps
Total Jitter for Data Rate < 600 Mbps 0.1 0.1 UI
tx Jitter - Emulated Differential I/O Standards with Three External Output Resistor Network Total Jitter for Data Rate 600 Mbps - 1.25 Gbps 300 325 ps
Total Jitter for Data Rate < 600 Mbps 0.2 0.25 UI
tDUTY Transmitter output clock duty cycle for both True and Emulated Differential I/O Standards 45 50 55 45 50 55 %
tRISE & tFALL True Differential I/O Standards 200 200 ps
Emulated Differential I/O Standards with three external output resistor networks 250 300 ps
TCCS True Differential I/O Standards 150 150 ps
Emulated Differential I/O Standards 300 300 ps
186 If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
187 The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
188 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
189 Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
190 Requires package skew compensation with PCB trace length.
191 Do not mix single-ended I/O buffer within LVDS I/O bank.
192 Chip-to-chip communication only with a maximum load of 5 pF.
193 The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity simulation is clean.
194 You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
195 When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.